A CMOS high-speed data recovery circuit using the matched delay sampling technique. - Jin-Ku Kang; Wentai Liu; Ralph K. Cavin III (IEEE J. Solid State Circuits, 1997)

A CMOS clock and data recovery with two-XOR phase-frequency detector circuit. - Jin-Ku Kang; Dong-Hee Kim (ISCAS (4), 2001)

A real time image processor for reproduction of gray levels in dark areas on plasma display panel (PDP). - Chang-Hoon Lee; Seung-Ho Park; Jin-Ku Kang; Choon-Woo Kim (IEEE Trans. Consumer Electron., 2002)

A clock recovery circuit using half-rate 4×-oversampling PD. - Hyung-Wook Jang; Sung-Sop Lee; Jin-Ku Kang (ISCAS (3), 2005)

3.125Gbps Reference-less Clock and Data Recovery using 4X Oversampling. - Sung-Sop Lee; Hyung-Wook Jang; Jin-Ku Kang (SoCC, 2005)

An 8B/10B encoder with a modified coding table. - Yong-Woo Kim; Jin-Ku Kang (APCCAS, 2008)

High-speed 8B/10B encoder design using a simplified coding table. - Yong-Woo Kim; Beomseok Shin; Jin-Ku Kang (IEICE Electron. Express, 2008)

A 2.7Gbps & 1.62Gbps dual-mode clock and data recovery for DisplayPort in 0.18μm CMOS. - Seungwon Lee; Tae-Ho Kim; Jae-Wook Yoo; Jin-Ku Kang (SoCC, 2009)

A 1.7Gbps DLL-based Clock Data Recovery in 0.35µm CMOS. - Sang-Ho Kim; Hyung-Min Park; Tae-Ho Kim; Jin-Ku Kang; Jin-Ho Kim; Jae-Youl Lee; Yoon-Kyung Choi; Myunghee Lee (SoCC, 2010)

A CMOS 5.4/3.24Gbps dual-rate clock and data recovery design for DisplayPort v1.2. - Jae-Wook Yoo; Tae-Ho Kim; Dong-Kyun Kim; Jin-Ku Kang (SoCC, 2010)

A DLL-based Clock Data Recovery with a modified input format. - Tae-Ho Kim; Sang-Ho Kim; Jin-Ku Kang (IEICE Electron. Express, 2010)

SSCG with Hershey-Kiss modulation profile using Dual Sigma-Delta modulators. - Hyung-Min Park; Hyun-Bae Jin; Jin-Ku Kang (IEICE Electron. Express, 2010)

A 4Gb/s adaptive FFE/DFE receiver with data-dependent jitter measurement. - Tae-Ho Kim; Jong-Seok Han; Sang-Soon Im; Jae-Young Jang; Jin-Ku Kang (ESSCIRC, 2011)

Low-power non-coherent data and power recovery circuit for implantable biomedical devices. - Benjamin P. Wilkerson; Tae-Ho Kim; Jin-Ku Kang (ISOCC, 2011)

Way-lookup buffer for low-power set-associative cache. - Sungjae Lee; Jin-Ku Kang; Inhwan Lee (IEICE Electron. Express, 2011)

A 4 Gb/s Adaptive FFE/DFE Receiver with a Data-Dependent Jitter Measurement. - Tae-Ho Kim; Yong-Hwan Moon; Jin-Ku Kang (IEICE Trans. Electron., 2011)

A non-coherent BPSK receiver with dual band filtering for implantable biomedical devices. - Benjamin P. Wilkerson; Jin-Ku Kang (ICECS, 2012)

An audio clock regenerator with a wide dividing ratio for HDMI. - Seung-Wuk Oh; Sang-Ho Kim; Jin-Ku Kang (ISCAS, 2012)

A 60 to 200MHz SSCG with approximate Hershey-Kiss modulation profile in 0.11µm CMOS. - Seung-Wook Oh; Hyung-Min Park; Joon-Hyup Seo; Jae-Young Jang; Gi-Yeol Bae; Jin-Ku Kang (ISOCC, 2012)

A high-speed adaptive linear equalizer with ISI level detection using periodic training pattern. - Jin-Cheol Seo; Tae-Ho Kim; Taek-Joon An; Kwan Yoon; Jin-Ku Kang (ISOCC, 2012)

A 1.62/2.7/5.4Gbps clock and data recovery circuit for DisplayPort 1.2. - Jin-Cheol Seo; Sang-Soon Im; Kwan-Hee Yoon; Seung-Wook Oh; Taek-Joon An; Gi-Yeol Bae; Jin-Ku Kang (SoCC, 2012)

A 10Gb/s adaptive equalizer with ISI level measurement. - Tae-Ho Kim; Jin-Cheol Seo; Yong-Sung Ahn; Jin-Ku Kang (IEICE Electron. Express, 2012)

Video denoising using overlapped motion compensation and advanced collaborative filtering. - Tae Hwan Lee; Jin-Ku Kang; Byung Cheol Song (J. Electronic Imaging, 2012)

Three-dimensional perception improvement using sharpness adjustment and hardware implementation. - Hak Gu Kim; Jin-Ku Kang; Byung Cheol Song (ICME Workshops, 2013)

A low power BPSK demodulator for wireless implantable biomedical devices. - Benjamin P. Wilkerson; Jin-Ku Kang (ISCAS, 2013)

An ultra-low power BPSK demodulator with dual band filtering for implantable biomedical devices. - Benjamin P. Wilkerson; Joon-Hyup Seo; Jin-Cheol Seo; Jin-Ku Kang (IEICE Electron. Express, 2013)

A 8.7mW 5-Gb/s clock and data recovery circuit with 0.18-µm CMOS. - Taek-Joon An; Kyung-Sub Son; Young-Jin Kim; In-Seok Kong; Jin-Ku Kang (ISCAS, 2014)

Avoiding noise frequency interference with binary phase pulse driving and CDS for capacitive TSP controller. - Yong-Sung Ahn; Taek-Joon Ahn; Kyongsu Lee; Jin-Ku Kang (IEICE Electron. Express, 2014)

A low jitter clock and data recovery with a single edge sensing Bang-Bang PD. - Taek-Joon Ahn; Sang-Soon Im; Yong-Sung Ahn; Jin-Ku Kang (IEICE Electron. Express, 2014)

A low-power CDR using dynamic CML latches and V/I converter merged with XOR for half-rate linear phase detection. - Taek-Joon Ahn; Kyung-Sub Son; Yong-Sung Ahn; Jin-Ku Kang (IEICE Electron. Express, 2014)

A 1.1 mW/Gb/s 10 Gbps half-rate clock-embedded transceiver for high-speed links in 65 nm CMOS. - Kyongsu Lee; Youngjin Kim; Kyung-Sub Son; Sangmin Lee; Jin-Ku Kang (IEICE Electron. Express, 2014)

Automatic SfM-Based 2D-to-3D Conversion for Multi-Object Scenes. - Hak Gu Kim; Jin-Ku Kang; Byung Cheol Song (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

A 2.2-mW 20-135-MHz False-Lock-Free DLL for Display Interface in 0.15-µm CMOS. - Yong-Hwan Moon; In-Seok Kong; Young-Soo Ryu; Jin-Ku Kang (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

On-chip jitter tolerance measurement technique for CDR circuits. - Kyung-Sub Son; Kyongsu Lee; Jin-Ku Kang (ISCAS, 2015)

Precise time-difference repetition for TDC with delay mismatch cancelling scheme. - In-Seok Kong; Kyung-Sub Son; Kyongsu Lee; Jin-Ku Kang (IEICE Electron. Express, 2015)

On-chip jitter tolerance measurement technique with independent jitter frequency modulation from VCO in CDR. - Kyung-Sub Son; Jin-Ku Kang (IEICE Electron. Express, 2015)

A Link Layer Design for DisplayPort Interface with State Machine Based Packet Processing. - Hyun-Bae Jin; Gi-Yeol Bae; Kwang-Hee Yoon; Tae-Ho Kim; Ji-Hoon Jang; Byung Cheol Song; Jin-Ku Kang (J. Signal Process. Syst., 2015)

A low jitter burst-mode clock and data recovery circuit with two symmetric VCO's. - Bum-Hee Choi; Kyung-Sub Son; Jin-Ku Kang (APCCAS, 2016)

A 200-Mb/s to 3-Gb/s wide-band referenceless CDR using bidirectional frequency detector. - Nguyen Huu Tho; Kyung-Sub Son; Kyongsu Lee; Jin-Ku Kang (ISOCC, 2016)

A burst-mode clock and data recovery circuit with two symmetric quadrature VCO's. - Bum-Hee Choi; Kyung-Sub Son; Taek-Joon An; Jin-Ku Kang (IEICE Electron. Express, 2016)

A 200 Mb/s∼3.2 Gb/s referenceless clock and data recovery circuit with bidirectional frequency detector. - Nguyen Huu Tho; Kyung-Sub Son; Jin-Ku Kang (IEICE Electron. Express, 2017)

A Two-Step Time-to-Digital Converter using Ring Oscillator Time Amplifier. - Min Kim; Kyung-Sub Son; Namhoon Kim; Chang Hang Rho; Jin-Ku Kang (ISOCC, 2018)

Design of a third-order delta-sigma TDC with error-feedback structure. - Seong-Mun An; Kyung-Sub Son; Taek-Joon An; Jin-Ku Kang (IEICE Electron. Express, 2019)

Eye-open monitor using two-dimensional counter value profile. - Kyung-Sub Son; Yong-Hwan Moon; Sanghun Baek; Namyong Kim; Taek-Joon An; Jin-Ku Kang (IEICE Electron. Express, 2019)

A 2.41-pJ/bit 5.4-Gb/s Dual-Loop Reference-Less CDR With Fully Digital Quarter-Rate Linear Phase Detector for Embedded DisplayPort. - Yong-Hwan Moon; Jae-Wook Yoo; Young-Soo Ryu; Sang-Ho Kim; Kyung-Sub Son; Jin-Ku Kang (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A 0.42-3.45 Gb/s Referenceless Clock and Data Recovery Circuit With Counter-Based Unrestricted Frequency Acquisition. - Kyung-Sub Son; Taek-Joon An; Yong-Hwan Moon; Jin-Ku Kang (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

Design of 20Gb/s PAM4 Transmitter with Maximum Transition Elimination and Transition Compensation Techniques. - Kyeong-Min Ko; Dohyeon Kwon; Jin-Ku Kang (ISOCC, 2021)

An 8 - 26 Gb/s Single Loop Reference-less CDR with Unrestricted Frequency Acquisition. - Hyung-Wook Lee; Kyeong-Min Ko; Jin-Ku Kang (ISOCC, 2021)

Two-step Time-to-Digital Converter using pulse-shifting time-difference repetition circuit. - Chang han Rho; Jin-Ku Kang; Jin Liu 004 (ISOCC, 2021)

A Resource Efficient Integer-Arithmetic-Only FPGA-Based CNN Accelerator for Real-Time Facial Emotion Recognition. - Jaemyung Kim; Jin-Ku Kang; Yongwoo Kim (IEEE Access, 2021)

A 0.32-2.7 Gb/s Reference-Less Continuous-Rate Clock and Data Recovery Circuit With Unrestricted and Fast Frequency Acquisition. - Nguyen Huu Tho; Ho-Joon Lee; Taek-Joon An; Jin-Ku Kang (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Filter Pruning Method for Inference Time Acceleration Based on YOLOX in Edge Device. - Jihun Jeon; Jin-Ku Kang; Yongwoo Kim (ISOCC, 2022)

A Low-Power Counter-based Digital CDR. - Hyun-In Kim; Jin-Ku Kang (ISOCC, 2022)

A Wide-range Low Power Quarter Rate Single Loop CDR. - Jin-Ho Kim; Jin-Ku Kang (ISOCC, 2022)

High-speed Serial Interface using PWAM Signaling Scheme. - Hwan-Ung Kim; Jin-Ku Kang (ISOCC, 2022)

An FPGA Implementation of CNN-based Compression Artifact Reduction. - Jaemyung Kim; Jin-Ku Kang; Yongwoo Kim (ISOCC, 2022)

A Design and Implementation of MIPI A-PHY RTS Layer. - Sang-Ung Shin; Jin-Ku Kang; Yongwoo Kim (ISOCC, 2022)

An Overhead-Reduced Key Coding Technique for High-Speed Serial Interface. - Jaepil Bak; Taek-Joon An; Youngwoo Kim; Jin-Ku Kang (IEEE Access, 2022)

Target Capacity Filter Pruning Method for Optimized Inference Time Based on YOLOv5 in Embedded Systems. - Jihun Jeon; Jaemyung Kim; Jin-Ku Kang; Sungtae Moon; Yongwoo Kim (IEEE Access, 2022)

A Low-Cost Fully Integer-Based CNN Accelerator on FPGA for Real-Time Traffic Sign Recognition. - Jaemyung Kim; Jin-Ku Kang; Yongwoo Kim (IEEE Access, 2022)

An FPGA-based Lightweight Deblocking CNN for Edge Devices. - Jaemyung Kim; Jin-Ku Kang; Yongwoo Kim (ISCAS, 2023)

A PAM-4 Baud-Rate CDR with High-Gain Phase Detector Using Shared Sampler. - Seoung-Geun Cho; Jin-Ku Kang (ISOCC, 2023)

A PAM-4 Receiver with Selective Reference Voltage Adaptation for Low Sensitivity to Sampler Voltage Variations. - Jeong-Mi Park; Jin-Ku Kang (ISOCC, 2023)

A ±0.48°C (3σ) Inaccuracy BJT-Based Temperature Sensor With 241 μs Conversion Time for Display Driver IC in 40 nm CMOS. - Yong-Sung Ahn; Jeong-Mi Park; Jin-Ku Kang; Jaehoon Jun (IEEE Access, 2023)

Fast, Efficient and Lightweight Compressed Image Super-Resolution Network for Edge Devices. - Jaemyung Kim; Jin-Ku Kang; Yongwoo Kim (AICAS, 2024)

An Efficient and Fast Filter Pruning Method for Object Detection in Embedded Systems. - Hyunjun Ko; Jin-Ku Kang; Yongwoo Kim (AICAS, 2024)

A 12-28 Gb/s Temperature Compensated PAM-4 Transmitter with 7B4Q Maximum Transition Avoidance and Fractional-Spaced FFE. - Sua Kim; Jin-Ku Kang (ISOCC, 2024)

A 2.5-12.3 Gb/s continuous-rate referenceless CDR with counter-based unlimited frequency detection. - Yujin Na; Jin-Ku Kang (ISOCC, 2024)

The hardware implementation of QARMA-64 with RoCC on FPGA for memory encryption. - Hyunjae Park; Jin-Ku Kang; Yongwoo Kim (ISOCC, 2024)

Autoencoder-based Knowledge Distillation For Quantized YOLO Detector. - Yugwon Seo; Jin-Ku Kang; Yongwoo Kim (ISOCC, 2024)

Adaptive Scaling Filter Pruning Method for Vision Networks With Embedded Devices. - Hyunjun Ko; Jin-Ku Kang; Yongwoo Kim (IEEE Access, 2024)

MASCAR: Multidomain Adaptive Spatial-Spectral Variable Compression Artifact Removal Network for Multispectral Remote Sensing Images. - Jaemyung Kim; Hyun-Ho Kim; Doo-Chun Seo; Jae-Heon Jeong; Jin-Ku Kang; Yongwoo Kim (IEEE Trans. Geosci. Remote. Sens., 2024)

1.4-8 Gb/s Low Power Quarter-Rate Single-Loop Referenceless CDR With Unlimited Capture Range. - Jin-Ho Kim; Tae Ho Kim; Hyung-Wook Lee; Jeong-Mi Park; Jin-Ku Kang (IEEE Trans. Circuits Syst. II Express Briefs, 2024)