A fully parallel learning neural network chip for real-time control. - Jin Liu 004; Martin A. Brooke (IJCNN, 1999)

A robust edge detector for motion detection. - Guangbin Zhang; Jin Liu 004 (ISCAS (4), 2002)

A CMOS feedforward neural-network chip with on-chip parallel learning for oscillation cancellation. - Jin Liu 004; Martin A. Brooke; Kenichi Hirotsu (IEEE Trans. Neural Networks, 2002)

Power-Optimal Simultaneous Buffer Insertion/Sizing and Wire Sizing. - Ruiming Li; Dian Zhou; Jin Liu 004; Xuan Zeng 001 (ICCAD, 2003)

A CMOS analog continuous-time FIR filter for 1Gbps cable equalizer. - Xiaofeng Lin 003; Jin Liu 004 (ISCAS (2), 2003)

Pulse extraction: a digital power spectrum estimation method for adaptation of Gbps equalizers. - Xiaofeng Lin 003; Guangbin Zhang; Jin Liu 004 (ISCAS (1), 2003)

An accurate current source with on-chip self-calibration circuits for low-voltage differential transmitter drivers. - Guangbin Zhang; Jin Liu 004; Sungyong Jung (ISCAS (2), 2003)

Steady-State Analysis of Nonlinear Circuits Using Discrete Singular Convolution Method. - Xin Zhou; Dian Zhou; Jin Liu 004; Ruiming Li; Xuan Zeng 001; Charles C. Chiang (DATE, 2004)

A CMOS impulse generator for UWB wireless communication systems. - Youngkyun Jeong; Sungyong Jung; Jin Liu 004 (ISCAS (4), 2004)

2.45 GHz power and data transmission for a low-power autonomous sensors platform. - Stefano Gregori; Yunlei Li; Huijuan Li; Jin Liu 004; Franco Maloberti (ISLPED, 2004)

Parasitic modeling and analysis for a 1-Gb/s CMOS laser driver. - Sungyong Jung; Martin A. Brooke; Nan M. Jokerst; Jin Liu 004; Youngjoong Joo (IEEE Trans. Circuits Syst. II Express Briefs, 2004)

A digital power spectrum estimation method for the adaptation of high-speed equalizers. - Xiaofeng Lin 003; Jin Liu 004 (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)

A continuous-time adaptive FIR equalizer with LNV-AIL delay line for 2.5Gb/s data communication. - Xiaofeng Lin 003; Hoi Lee; Jin Liu 004 (CICC, 2005)

Power-optimal simultaneous buffer insertion/sizing and uniform wire sizing for single long wires. - Ruiming Li; Dian Zhou; Jin Liu 004; Xuan Zeng 001 (ISCAS (1), 2005)

A CMOS 0.25-μm continuous-time FIR filter with 125 ps per tap delay as a fractionally spaced receiver equalizer for 1-gb/s data transmission. - Xiaofeng Lin 003; Sooping Saw; Jin Liu 004 (IEEE J. Solid State Circuits, 2005)

Power-optimal simultaneous buffer insertion/sizing and wire sizing for two-pin nets. - Ruiming Li; Dian Zhou; Jin Liu 004; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

A 0.8V 1.52MHz MSVC Relaxation Oscillator with Inverted Mirror Feedback Reference for UHF RFID. - Raymond E. Barnett; Jin Liu 004 (CICC, 2006)

A 2.5- to 3.5-Gb/s Adaptive FIR Equalizer With Continuous-Time Wide-Bandwidth Delay Line in 0.25-$muhbox m$CMOS. - Xiaofeng Lin 003; Jin Liu 004; Hoi Lee; Hao Liu (IEEE J. Solid State Circuits, 2006)

An accurate current source with on-chip self-calibration circuits for low-voltage current-mode differential drivers. - Guangbin Zhang; Sooping Saw; Jin Liu 004; Scott Sterrantino; David K. Johnson; Sungyong Jung (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

An EEPROM Programming Controller for Passive UHF RFID Transponders With Gated Clock Regulation Loop and Current Surge Control. - Raymond E. Barnett; Jin Liu 004 (IEEE J. Solid State Circuits, 2008)

Gigabit transceivers and building blocks. - Jin Liu 004; Jim Buckwalter (CICC, 2009)

A 18mW 10Gbps continuous-time FIR equalizer for wired line data communications in 0.12µm CMOS. - Hao Liu; Jin Liu 004; Robert Payne; Cy Cantrell; Mark Morgan (CICC, 2009)

A RF to DC Voltage Conversion Model for Multi-Stage Rectifiers in UHF RFID Transponders. - Raymond E. Barnett; Jin Liu 004; Steve Lazar (IEEE J. Solid State Circuits, 2009)

Bulk Voltage Trimming Offset Calibration for High-Speed Flash ADCs. - Junjie Yao; Jin Liu 004; Hoi Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

An open-loop 10GHz 8-phase clock generator in 65nm CMOS. - Xiaochen Yang; Jin Liu 004 (CICC, 2011)

A 5-MHz 91% Peak-Power-Efficiency Buck Regulator With Auto-Selectable Peak- and Valley-Current Control. - Mengmeng Du; Hoi Lee; Jin Liu 004 (IEEE J. Solid State Circuits, 2011)

Ground Switching Load Modulation With Ground Isolation for Passive HF RFID Transponders. - Yunlei Li; Jin Liu 004; Hoi Lee (IEEE Trans. Very Large Scale Integr. Syst., 2012)

A 10GS/s 6b time-interleaved ADC with partially active flash sub-ADCs. - Xiaochen Yang; Robert Payne; Jin Liu 004 (CICC, 2013)

Study of ADC resolution and bandwidth requirement tradeoffs for high-speed data communications. - Jin Liu 004; Vinod Mukundagiri (MWSCAS, 2013)

A 5-Gb/s Automatic Sub-Bit Between-Pair Skew Compensator for Parallel Data Communications in 0.13-µm CMOS. - Yuxiang Zheng; Jin Liu 004; Robert Payne; Mark Morgan; Hoi Lee (IEEE Trans. Very Large Scale Integr. Syst., 2013)

A 10 GS/s 6 b Time-Interleaved Partially Active Flash ADC. - Xiaochen Yang; Jin Liu 004 (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

A Metastability Error Detection and Reduction Technique for Partially Active Flash ADCs. - Xiaochen Yang; Guoping Cui; Yang Zhang; Jiajun Ren; Jin Liu 004 (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

A New Receiver Architecture for MIMO Beam-Forming Applications. - Yucheng Dai; Yahia R. Ramadan; Hlaing Minn; Jiu Xiong; Jin Liu 004; Alan Gatherer (GLOBECOM, 2017)

An open-loop 28GHz 16-phase clock generator in 28nm CMOS. - Jiu Xiong; Jin Liu 004; Yucheng Dai; Hlaing Minn (MWSCAS, 2017)

An efficient and robust method to determine the optimal tap coefficients of high speed FIR equalizer. - Guanming Huang; Donesh Gillin; Dian Zhou; Jin Liu 004; Xuan Zeng 001; Po-Yu Kuo (Sci. China Inf. Sci., 2017)

High-Speed ADC Quantization with Overlapping Metastability Zones. - Jiajun Ren; Jiu Xiong; Jin Liu 004 (MWSCAS, 2018)

ADC Quantization with Overlapping Metastability Zones and Dual Reference Calibration. - Jiajun Ren; Jiu Xiong; Jin Liu 004 (MWSCAS, 2019)

An 8-b 2b/cycle Asynchronous SAR ADC with Capacitive Divider Based RC-DAC. - Jiu Xiong; Jiajun Ren; Jin Liu 004 (MWSCAS, 2019)

A High-Efficiency Low-Profile Zero-Voltage Transition Synchronous Non-Inverting Buck-Boost Converter With Auxiliary-Component Sharing. - Lin Cong; Jin Liu 004; Hoi Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A 9 - 45V Input 2MHz 3-Switch ZVS Step-up / -down Hybrid Converter with 5x Volume Reduction. - Chen Chen; Jin Liu 004; Hoi Lee (CICC, 2020)

A 5-100V Input Low-Profile Adaptive Delay Compensated Hysteretic LED Driver with Enhanced Current Accuracy. - Qi Cheng 005; Jin Liu 004; Hoi Lee (CICC, 2021)

Two-step Time-to-Digital Converter using pulse-shifting time-difference repetition circuit. - Chang han Rho; Jin-Ku Kang; Jin Liu 004 (ISOCC, 2021)

A 2-MHz 9-45-V Input High-Efficiency Three-Switch ZVS Step-Up/-Down Hybrid Converter. - Chen Chen; Jin Liu 004; Hoi Lee (IEEE J. Solid State Circuits, 2021)

A 1.2-A Dual-Output SC DC-DC Regulator With Continuous Gate-Drive Modulation Achieving ≤0.01-mV/mA Cross Regulation. - Zhe Hua; Qi Cheng 005; Jin Liu 004; Hoi Lee (IEEE J. Solid State Circuits, 2021)

A Diode-Based D-2D DAC Architecture with Leakage Current Compensation for Ultra-low Power Application. - Jesse Coulon; Jin Liu 004 (ISCAS, 2022)

A 200mA-Load 0.62fs-FOM Active-Capacitor-Assisted Dual-loop Output Capacitorless Low-Dropout Regulator in Standard 65nm CMOS. - Weijie Han; Ziyang Luo; Chen Chen; Jin Liu 004; Hoi Lee (ISCAS, 2022)

A 3rd Order CT-ΣΔ Modulator with a Hybrid Loop Filter Employing Passive and Continuous-Time Delay Based Integrators. - Jiu Xiong; Jeniffer Zhao; Jin Liu 004; Hoi Lee (ISCAS, 2022)

A 2-5MHz Multiple DC Output Hybrid Boost Converter with Scalable CR Boosting Scheme Achievi 1 ng 91% Efficie 1 ncy at a Conversion Ratio of 12. - Chen Chen; Jin Liu 004; Hoi Lee (ISSCC, 2022)

A 2.5-5MHz 87% Peak Efficiency 48V-to-1V Integrated Hybrid DC-DC Converter Adopting Ladder SC Network with Capacitor-Assisted Dual-Inductor Filtering. - Chen Chen; Jin Liu 004; Hoi Lee (ISSCC, 2022)

A Wide-Input-Range Low-Profile Adaptive Delay Compensated Hysteretic LED Driver With Enhanced Current Accuracy. - Qi Cheng 005; Jin Liu 004; Hoi Lee (IEEE J. Solid State Circuits, 2022)

A Continuous-Time Sigma-Delta Modulator With Continuous-Time Delay-Based Integrator. - Jiu Xiong; Jin Liu 004; Hoi Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 40.68-MHz Active Rectifier With Cycle-Based On-/Off-Delay Compensation for High-Current Biomedical Implants. - Ziyang Luo; Jin Liu 004; Hoi Lee (IEEE J. Solid State Circuits, 2023)

A High-Efficiency 40.68-MHz Single-Stage Dual-Output Regulating Rectifier With ZVS and Synchronous PFM Control for Wireless Powering. - Ziyang Luo; Jin Liu 004; Hoi Lee (IEEE J. Solid State Circuits, 2024)