A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/s bandwidth. - Jei-Hwan Yoo; Chang-Hyun Kim; Kyu-Chan Lee; Kye-Hyun Kyung; Seung-Moon Yoo; Jung-Hwa Lee; Moon-Hae Son; Jin-Man Han; Bok-Moon Kang; Ejaz Haq; Sang-Bo Lee; Jai-Hoon Sim; et al. (IEEE J. Solid State Circuits, 1996)

A 7MB/s 64Gb 3-bit/cell DDR NAND flash memory in 20nm-node technology. - Ki-Tae Park; Ohsuk Kwon; Sangyong Yoon; Myung-Hoon Choi; In-Mo Kim; Bo-Geun Kim; Min-Seok Kim; Yoon-Hee Choi; Seung-Hwan Shin; Youngson Song; Joo-Yong Park; Jae-Eun Lee; et al. (ISSCC, 2011)

A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology. - Daeyeal Lee; Ik Joon Chang; Sangyong Yoon; Joonsuc Jang; Dong-Su Jang; Wook-Ghee Hahn; Jong-Yeol Park; Doo-Gon Kim; Chiweon Yoon; Bong-Soon Lim; ByungJun Min; Sung-Won Yun; et al. (ISSCC, 2012)

A new 3-bit programming algorithm using SLC-to-TLC migration for 8MB/s high performance TLC NAND flash memory. - Seung-Hwan Shin; Dong-Kyo Shim; Jaeyong Jeong; Ohsuk Kwon; Sangyong Yoon; Myung-Hoon Choi; Tae-Young Kim; Hyun Wook Park; Hyun-Jun Yoon; Youngsun Song; Yoon-Hee Choi; Sang-Won Shim; et al. (VLSIC, 2012)

A 21 nm High Performance 64 Gb MLC NAND Flash Memory With 400 MB/s Asynchronous Toggle DDR Interface. - Chulbum Kim; Jinho Ryu; Tae-Sung Lee; Hyunggon Kim; Jaewoo Lim; Jaeyong Jeong; Seonghwan Seo; Hongsoo Jeon; Bokeun Kim; Inyoul Lee; Dooseop Lee; Pansuk Kwak; et al. (IEEE J. Solid State Circuits, 2012)

F2: VLSI power-management techniques: Principles and applications. - Leland Chang; Shannon Morton; Ken Chang; Jin-Man Han; Piero Malcovati; Vladimir Stojanovic (ISSCC, 2013)

Session 12 overview: Non-volatile memory solutions. - Jin-Man Han; Daniele Vimercati (ISSCC, 2013)

Adaptive Multi-Pulse Program Scheme Based on Tunneling Speed Classification for Next Generation Multi-Bit/Cell NAND FLASH. - Yong-Sung Cho; Il-Han Park; Sangyong Yoon; Nam-Hee Lee; Sang-Hyun Joo; Ki-Whan Song; Kihwan Choi; Jin-Man Han; Kyehyun Kyung; Young-Hyun Jun (IEEE J. Solid State Circuits, 2013)

19.5 Three-dimensional 128Gb MLC vertical NAND Flash-memory with 24-WL stacked layers and 50MB/s high-speed programming. - Ki-Tae Park; Jin-Man Han; Dae-Han Kim; Sangwan Nam; Kihwan Choi; Minsu Kim 004; Pansuk Kwak; Doosub Lee; Yoon-Hee Choi; Kyung-Min Kang; Myung-Hoon Choi; Dong-Hun Kwak; et al. (ISSCC, 2014)

Three-Dimensional 128 Gb MLC Vertical nand Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming. - Ki-Tae Park; Sangwan Nam; Dae-Han Kim; Pansuk Kwak; Doosub Lee; Yoon-Hee Choi; Myung-Hoon Choi; Dong-Hun Kwak; Doo-Hyun Kim; Minsu Kim 004; Hyun Wook Park; Sang-Won Shim; et al. (IEEE J. Solid State Circuits, 2015)

Session 7 overview: Nonvolatile memory solutions. - Sungdae Choi; Jin-Man Han (ISSCC, 2016)