An FPGA Implementation of Array LDPC Decoder. - Jin Sha; Minglun Gao; Zhongjin Zhang; Li Li 003; Zhongfeng Wang 001 (APCCAS, 2006)

LDPC Decoder Design for IEEE 802.15 Standard. - Jin Sha; Jun Lin 001; Li Li 003; Minglun Gao; Zhongfeng Wang 001 (ISCAS, 2009)

Area-efficient Reed-Solomon Decoder Design for 10-100 Gb/s Applications. - Bo Yuan 001; Li Li 003; Jin Sha; Zhongfeng Wang 001 (ISCAS, 2009)

An improved min-sum based column-layered decoding algorithm for LDPC codes. - Jun Lin 001; Jin Sha; Zhongfeng Wang 001; Li Li 003 (SiPS, 2009)

Efficient Shuffle Network Architecture and Application for WiMAX LDPC Decoders. - Jun Lin 001; Zhongfeng Wang 001; Li Li 003; Jin Sha; Minglun Gao (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

Decoder Design for RS-Based LDPC Codes. - Jin Sha; Jun Lin 001; Zhongfeng Wang 001; Li Li 003; Minglun Gao (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

Area-efficient reed-solomon decoder design for optical communications. - Bo Yuan 001; Zhongfeng Wang 001; Li Li 003; Minglun Gao; Jin Sha; Chuan Zhang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

LDPC decoder design for high rate wireless personal area networks. - Jin Sha; Jun Lin 001; Zhongfeng Wang 001; Li Li 003; Minglun Gao (IEEE Trans. Consumer Electron., 2009)

An improved scaled DCT architecture. - Zhigang Wu; Jin Sha; Zhongfeng Wang 001; Li Li 003; Minglun Gao (IEEE Trans. Consumer Electron., 2009)

Multi-Gb/s LDPC Code Design and Implementation. - Jin Sha; Zhongfeng Wang 001; Minglun Gao; Li Li 003 (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Low power decoder design for QC-LDPC codes. - Kai He; Jin Sha; Li Li 003; Zhongfeng Wang 001 (ISCAS, 2010)

Layered decoding for non-binary LDPC codes. - Shuai Zhou; Jin Sha; Li Li 003; Zhongfeng Wang 001 (ISCAS, 2010)

Efficient Decoder Design for Nonbinary Quasicyclic LDPC Codes. - Jun Lin 001; Jin Sha; Zhongfeng Wang 001; Li Li 003 (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

An Efficient VLSI Architecture for Nonbinary LDPC Decoders. - Jun Lin 001; Jin Sha; Zhongfeng Wang 001; Li Li 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

Flexible LDPC Decoder Design for Multigigabit-per-Second Applications. - Chuan Zhang 001; Zhongfeng Wang 001; Jin Sha; Li Li 003; Jun Lin 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Memory efficient decoder design of nonbinary LDPC codes. - Kai He; Jin Sha; Zhongfeng Wang 001 (ISOCC, 2011)

Efficient Reed-Solomon based LDPC decoders. - Chuan Zhang 001; Sang-Min Kim; Jin Sha (ISOCC, 2011)

Memory efficient column-layered decoder design for non-binary LDPC codes. - Kai He; Jin Sha; Zhongfeng Wang 001 (ISCAS, 2012)

Efficient network for non-binary QC-LDPC decoder. - Chuan Zhang 001; Jin Sha (ISCAS, 2012)

Efficient EMS decoding for non-binary LDPC codes. - Leixin Zhou; Jin Sha; Zhongfeng Wang 001 (ISOCC, 2012)

Nonbinary LDPC Code Decoder Architecture With Efficient Check Node Processing. - Kai He; Jin Sha; Zhongfeng Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

Unified Architecture for Reed-Solomon Decoder Combined With Burst-Error Correction. - Li Li 003; Bo Yuan 001; Zhongfeng Wang 001; Jin Sha; Hongbing Pan; Weishan Zheng (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Memory efficient EMS decoding for non-binary LDPC codes. - Leixin Zhou; Jin Sha; Yun Chen 001; Zhongfeng Wang 001 (ISCAS, 2013)

Hardware architecture for list successive cancellation polar decoder. - Chuan Zhang 001; Xiaohu You 001; Jin Sha (ISCAS, 2014)

Efficient symbol reliability based decoding for QCNB-LDPC codes. - Leixin Zhou; Jin Sha; Yun Chen 001; Chuan Zhang 001; Zhongfeng Wang 001 (ISCAS, 2014)

A more accurate circuit model for CMOS Hall cross with non-linear resistors and JFETs. - Fei Lyu 002; Zhenduo Zhu; Zhenfei Lu; Li Li 003; Jin Sha; Hongbing Pan; Yutong Bi (ISIC, 2014)

Effects of Circuit Parameters on Dynamics of Current-Mode-Pulse-Train-Controlled Buck Converter. - Jin Sha; Jianping Xu; Bocheng Bao; Tiesheng Yan (IEEE Trans. Ind. Electron., 2014)

Variable-On-Time-Controlled Critical-Conduction-Mode Flyback PFC Converter. - Tiesheng Yan; Jianping Xu; Fei Zhang; Jin Sha; Zheng Dong (IEEE Trans. Ind. Electron., 2014)

A stage-reduced low-latency successive cancellation decoder for polar codes. - Xing Liu; Jin Sha; Chuan Zhang 001; Zhongfeng Wang 001 (DSP, 2015)

Tail-biting code: A modification to staircase code for high-speed networking. - Guanghui Hu; Jin Sha (SiPS, 2015)

Performance Comparison of Cross-Like Hall Plates with Different Covering Layers. - Fei Lyu 002; Zhenyan Zhang; Eng-Huat Toh; Xinfu Liu; Yinjie Ding; Yifan Pan; Chengjie Li; Li Li 003; Jin Sha; Hongbing Pan (Sensors, 2015)

Control Pulse Combination-Based Analysis of Pulse Train Controlled DCM Switching DC-DC Converters. - Jin Sha; Jianping Xu; Shu Zhong; Shuhan Liu; Lijun Xu (IEEE Trans. Ind. Electron., 2015)

A high throughput belief propagation decoder architecture for polar codes. - Jun Lin 001; Jin Sha; Li Li 003; Chenrong Xiong; Zhiyuan Yan 001; Zhongfeng Wang 001 (ISCAS, 2016)

Stage-combined belief propagation decoding of polar codes. - Jin Sha; Jun Lin 001; Zhongfeng Wang 001 (ISCAS, 2016)

Beyond 100Gbps Encoder Design for Staircase Codes. - Guanghui Hu; Jin Sha; Zhongfeng Wang 001 (SiPS, 2016)

An Efficient FPGA Implementation for 2-D MUSIC Algorithm. - Kai Huang; Jin Sha; Wei Shi; Zhongfeng Wang 001 (Circuits Syst. Signal Process., 2016)

Influences of an Aluminum Covering Layer on the Performance of Cross-Like Hall Devices. - Fei Lyu 002; Xinfu Liu; Yinjie Ding; Eng-Huat Toh; Zhenyan Zhang; Yifan Pan; Zhen Wang; Chengjie Li; Li Li 003; Jin Sha; Hongbing Pan (Sensors, 2016)

A Peak-Capacitor-Current Pulse-Train-Controlled Buck Converter With Fast Transient Response and a Wide Load Range. - Jin Sha; Duo Xu 002; Yiming Chen 006; Jianping Xu; Barry W. Williams (IEEE Trans. Ind. Electron., 2016)

Joint detection and decoding for non-binary LDPC coded MIMO systems. - Yiqian Cai; Jin Sha; Shusen Jing; Xiaohu You 001; Chuan Zhang 001 (ASICON, 2017)

Joint detection and decoding for polar-coded OFDM-IDMA systems. - Xiangyun Deng; Jin Sha; Xiaotian Zhou; Xiaohu You 001; Chuan Zhang 001 (ASICON, 2017)

The VLSI architecture for channel estimation based on ADMA. - Xiaozhen Liu; Hongxiang Xie; Jin Sha; Feifei Gao; Shi Jin 002; Xiaohu You 001; Chuan Zhang 001 (ASICON, 2017)

Automatic classification of leukocytes using deep neural network. - Wei Yu; Jing Chang; Cheng Yang; Limin Zhang; Han Shen; Yongquan Xia; Jin Sha (ASICON, 2017)

An efficient implementation of 2D convolution in CNN. - Jing Chang; Jin Sha (IEICE Electron. Express, 2017)

An access pattern based adaptive mapping function for GPGPU scratchpad memory. - Feng Han 008; Li Li 003; Kun Wang 005; Fan Feng; Hongbing Pan; Jin Sha; Jun Lin 001 (IEICE Electron. Express, 2017)

Frozen bits selection for polar codes based on simulation and BP decoding. - Jingbo Liu; Jin Sha (IEICE Electron. Express, 2017)

Optimized sorting network for successive cancellation list decoding of polar codes. - Kun Wang 005; Li Li 003; Feng Han 008; Fan Feng; Jun Lin 001; Yuxiang Fu; Jin Sha (IEICE Electron. Express, 2017)

High-Speed Parallel LFSR Architectures Based on Improved State-Space Transformations. - Guanghui Hu; Jin Sha; Zhongfeng Wang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Polar-coded forward error correction for MLC NAND flash memory. - Haochuan Song; Jen-Chien Fu; Shih-Jia Zeng; Jin Sha; Zaichen Zhang; Xiaohu You 001; Chuan Zhang 001 (Sci. China Inf. Sci., 2018)

Polar-Coded Forward Error Correction for MLC NAND Flash Memory Polar FEC for NAND Flash Memory. - Haochuan Song; Frankie Fu; Cloud Zeng; Jin Sha; Zaichen Zhang; Xiaohu You 001; Chuan Zhang 001 (CoRR, 2018)

4.7-Gb/s LDPC Decoder on GPU. - Jinyang Yuan; Jin Sha (IEEE Commun. Lett., 2018)

A low complexity LDPC-BCH concatenated decoder for NAND flash memory. - Zhongjie Chen; Jin Sha; Chuan Zhang 001; Feng Yan (IEICE Electron. Express, 2018)

Improved gradient descent bit flipping decoder for LDPC codes on BSC channel. - Dao Ren; Jin Sha (IEICE Electron. Express, 2018)

Multi-column parallel QC-LDPC decoder architecture for NAND flash memory. - Wei Shen; Cheng Chen; Jin Sha (IEICE Electron. Express, 2018)

Dispersed Array LDPC Codes and Decoder Architecture for NAND Flash Memory. - Wei Shao; Jin Sha; Chuan Zhang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A Stage-Combined Belief Propagation Decoder for Polar Codes. - Jin Sha; Jingbo Liu; Jun Lin 001; Zhongfeng Wang 001 (J. Signal Process. Syst., 2018)

Symbol-Based Algorithms for Decoding Binary LDPC Codes with Higher-Order Modulations. - Jingbo Liu; Jingyang Yuan; Jin Sha (ISCAS, 2019)

Prune Deep Neural Networks With the Modified L1/2 Penalty. - Jing Chang; Jin Sha (IEEE Access, 2019)

FPGA-based low-complexity high-throughput real-time hardware accelerator for robust watermarking. - Hangqi Ge; Jin Sha (J. Real Time Image Process., 2019)

Satellite Observations of Wind Wake and Associated Oceanic Thermal Responses: A Case Study of Hainan Island Wind Wake. - Jin Sha; Xiao-Ming Li 005; Xue'en Chen; Tianyu Zhang (Remote. Sens., 2019)

Joint Detection and Decoding of Polar-Coded OFDM-IDMA Systems. - Xiangyun Deng; Jin Sha; Xiaotian Zhou; Yuxiang Fu; Zaichen Zhang; Xiaohu You 001; Chuan Zhang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Efficient Channel Estimator With Angle-Division Multiple Access. - Xiaozhen Liu; Jin Sha; Hongxiang Xie; Feifei Gao; Shi Jin 002; Zaichen Zhang; Xiaohu You 001; Chuan Zhang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Evaluation and Suppression of a Low-Frequency Output Voltage Ripple of a Single-Stage AC-DC Converter Based on an Output Impedance Model. - Yaping Cai; Jianping Xu; Ping Yang; Jiahui Wu; Jin Sha (IEEE Trans. Ind. Electron., 2019)

A Digital Pulse Train Controlled High Power Factor DCM Boost PFC Converter Over a Universal Input Voltage Range. - Huan Luo; Jianping Xu; Yiwen Luo; Jin Sha (IEEE Trans. Ind. Electron., 2019)

Pulse Train Control Strategy for CCM Boost PFC Converter With Improved Dynamic Response and Unity Power Factor. - Huan Luo; Jianping Xu; Dayin He; Jin Sha (IEEE Trans. Ind. Electron., 2020)

Efficient HLS Implementation of Fast Linear Discriminant Analysis Classifier. - Dezhi Peng; Jin Sha (IEEE Embed. Syst. Lett., 2021)

Embedded Bidirectional Buck-Boost Converter in Half Bridge Class-D Audio Amplifier for Suppressing Bus Voltage Pumping. - Rui Huang; Duo Xu 002; Feiming Liu; Jin Sha; Jianping Xu (IEEE Trans. Ind. Electron., 2022)

RF Fingerprinting Identification Based on Spiking Neural Network for LEO-MIMO Systems. - Qi Jiang; Jin Sha (IEEE Wirel. Commun. Lett., 2023)

An Adaptive Chase-Pyndiah Algorithm for Turbo Product Codes. - Shangpeng Deng; Zhiyuan Xiao; Jin Sha; Zhongfeng Wang 001 (IEEE Commun. Lett., 2023)

Discrete Extended-Phase-Shift Control for Dual-Active-Bridge DC-DC Converter With Fast Dynamic Response. - Jin Sha; Lirong Chen; Guohua Zhou (IEEE Trans. Ind. Electron., 2023)

An Improved Critical Set for List Decoding of Polar Codes. - Heng Liu; Jin Sha; Xiumin Wang (IEEE Commun. Lett., 2023)

The Use of SNN for Ultralow-Power RF Fingerprinting Identification With Attention Mechanisms in VDES-SAT. - Qi Jiang; Jin Sha (IEEE Internet Things J., 2023)

A Discrete Average Current Mode Control CCM Boost PFC Converter With Hybrid Pulse Train Modulation and Dual Edge Modulation. - Jin Sha; Jiahao Hu; Honghao Wei (IEEE Trans. Ind. Electron., 2023)

1+1 <2: Efficient Automatic Standard Cell Sharing Between Digital VLSI Designs for Area Saving. - Lang Feng 001; Jin Sha; Zhongfeng Wang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Efficient UAV Identification Leveraging Multi-Resolution Analysis and Multi-Scale ResNet. - Zhenxin Cai; Jin Sha; Yu Wang 078; Guan Gui 001 (VTC Spring, 2024)

Toward Intelligent Lightweight and Efficient UAV Identification With RF Fingerprinting. - Zhenxin Cai; Yu Wang 078; Qi Jiang; Guan Gui 001; Jin Sha (IEEE Internet Things J., 2024)

Radio Frequency Fingerprint Identification Based on Variational Autoencoder for GNSS. - Qi Jiang; Jin Sha (IEEE Geosci. Remote. Sens. Lett., 2024)

RF Fingerprinting Identification in Low SNR Scenarios for Automatic Identification System. - Qi Jiang; Jin Sha (IEEE Trans. Wirel. Commun., 2024)

Principle, Design, and Analysis of a Novel Discrete Pulse Control for Single-Phase Voltage Source Inverter. - Jin Sha; Honghao Wei; Jiahao Hu (IEEE Trans. Ind. Electron., 2024)

Hybrid Modulation-Based Discrete Extended-Phase-Shift Control for Dual-Active-Bridge DC-DC Converter. - Jin Sha; Jinsong Shen; Han Wang; Gaofeng Qiu; Yuebing Sun (IEEE Trans. Ind. Electron., 2024)

Toward Robust Radio Frequency Fingerprint Identification via Adaptive Semantic Augmentation. - Zhenxin Cai; Yu Wang 078; Guan Gui 001; Jin Sha (IEEE Trans. Inf. Forensics Secur., 2025)

Radio Frequency Fingerprint Identification Using Conditional Generative Adversarial Network for SAT-AIS. - Qi Jiang; Jin Sha (IEEE Trans. Aerosp. Electron. Syst., 2025)

Physical Layer Authentication via Conditional Variational Auto-Encoder for AIS. - Qi Jiang; Jin Sha (IEEE Trans. Green Commun. Netw., 2025)

An Energy-Efficient FPGA Accelerator for Swin Transformer. - Yuefei Wang; Wendong Mao; Huihong Shi; Jin Sha; Zhongfeng Wang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2025)

A CPU+FPGA OpenCL Heterogeneous Computing Platform for Multi-Kernel Pipeline. - Yuefei Wang; Wendong Mao; Lang Feng 001; Jin Sha; Zhongfeng Wang 001 (ACM Trans. Design Autom. Electr. Syst., 2025)

Channel-Resilient and Low-Power Radio Frequency Fingerprint Identification for VDES-SAT. - Qi Jiang; Jin Sha (IEEE Trans. Cogn. Commun. Netw., 2025)