A robust over-the-cell channel router. - Lih-Der Chang; Pei-Yung Hsiao; Jin-Tai Yan; Paul-Waie Shew (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Routability crossing distribution and floating terminal assignment of T-type junction region. - Jin-Tai Yan; Pei-Yung Hsiao (Great Lakes Symposium on VLSI, 1994)

Efficient Algorithms for Two and Three-Layer Over-the-Cell Channel Routing. - Paul-Waie Shew; Jin-Tai Yan; Pei-Yung Hsiao; Yong-Ching Lim (ISCAS, 1994)

Region Definition of Minimizing the Number of Switchboxes and Ordering Assignment. - Jin-Tai Yan; Pei-Yung Hsiao (ISCAS, 1994)

A Fuzzy Clustering Algorithm for Graph Bisection. - Jin-Tai Yan; Pei-Yung Hsiao (Inf. Process. Lett., 1994)

Region definition and ordering assignment with the minimization of the number of switchboxes. - Jin-Tai Yan (ASP-DAC, 1995)

An Efficient Heuristic Approach on Minimizing the Number of Feedthrough Cells in Standard Cell Placement. - Jin-Tai Yan (Great Lakes Symposium on VLSI, 1995)

Connection-oriented net model and fuzzy clustering techniques for K-way circuit partitioning. - Jin-Tai Yan (ICCD, 1995)

A new fuzzy-clustering-based approach for two-way circuit partitioning. - Jin-Tai Yan; Pei-Yung Hsiao (VLSI Design, 1995)

An Optimal ILP Formulation for Minimixing the Number of Feedthrough Cells in Standard Cell Placement. - Jin-Tai Yan (Great Lakes Symposium on VLSI, 1996)

A simple yet effective genetic approach for the orientation assignment on cell-based layout. - Jin-Tai Yan (VLSI Design, 1996)

Minimizing the number of switchboxes for region definition and ordering assignment. - Jin-Tai Yan; Pei-Yung Hsiao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

An O(NlogN) Algorithm for Region Definition Using Channels/Switchboxes and Ordering Assignment. - Jin-Tai Yan; Pei-Yung Hsiao (VLSI Design, 1996)

Routing Space Estimation and Assignment for Macro-Cell Placement. - Jin-Tai Yan (J. Circuits Syst. Comput., 1998)

An improved optimal algorithm for bubble-sorting-basednon-Manhattan channel routing. - Jin-Tai Yan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

An efficient cut-based algorithm on minimizing the number of L-shaped channels for safe routing ordering. - Jin-Tai Yan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Routability Crossing Distribution and Floating Pin Assignment for T-type Junction Region. - Jin-Tai Yan (VLSI Design, 1999)

An ILP Formulation for Minimizing the Number of Feedthrough Cells in a Standard Cell Placement. - Jin-Tai Yan (VLSI Design, 1999)

Three-layer bubble-sorting-based nonManhattan channel routing. - Jin-Tai Yan (ACM Trans. Design Autom. Electr. Syst., 2000)

Printed circuit board routing and package layout codesign. - Shuenn-Shi Chen; Wang-Dauh Tseng; Jin-Tai Yan; Sao-Jie Chen (APCCAS (1), 2002)

Timing-constrained congestion-driven global routing. - Jin-Tai Yan; Shun-Hua Lin (ASP-DAC, 2004)

LB-packing-based floorplan design on DBL representation. - Jin-Tai Yan; Kai-Ping Lin; Yue-Fong Luo (ICECS, 2005)

Floorplan-aware Steiner tree reconstruction for optimal buffer insertion. - Jin-Tai Yan; Chia-Fang Lee; Tzu-Ya Wang (ICECS, 2005)

Probabilistic congestion prediction in hierarchical quad-grid model. - Jin-Tai Yan; Yen-Hsiang Chen; Chia-Wei Wu (ISCAS (2), 2005)

Decoupling capacitance allocation in noise-aware floorplanning based on DBL representation. - Jin-Tai Yan; Kai-Ping Lin; Yen-Hsiang Chen (ISCAS (3), 2005)

Wiring area optimization in floorplan-aware hierarchical power grids. - Jin-Tai Yan; Chia-Wei Wu; Yen-Hsiang Chen (ISCAS (2), 2005)

Timing-driven Steiner tree construction based on feasible assignment of hidden Steiner points. - Jin-Tai Yan; Tzu-Ya Wang; Yu-Cheng Lee (ISCAS (2), 2005)

Timing-Constrained Flexibility-Driven Routing Tree Construction. - Jin-Tai Yan; Yen-Hsiang Chen; Chia-Fang Lee (IEICE Trans. Inf. Syst., 2005)

Width and Timing-Constrained Wire Sizing for Critical Area Minimization. - Jin-Tai Yan; Bo-Yi Chiang; Shi-Qin Huang (APCCAS, 2006)

Optimal Network Analysis in Hierarchical Power Quad-Grids. - Jin-Tai Yan; Zhi-Wei Chen; Chia-Wei Wu; Ming-Yuen Wu (APCCAS, 2006)

Yield-Driven Redundant Via Insertion Based on Probabilistic Via-Connection Analysis. - Jin-Tai Yan; Bo-Yi Chiang; Zhi-Wei Chen (ICECS, 2006)

Area-Driven White Space Distribution for Detailed Floorplan Design. - Jin-Tai Yan; Zhi-Wei Chen; Ming-Yuen Wu (ICECS, 2006)

Timing-constrained yield-driven wire sizing for critical area minimization. - Jin-Tai Yan; Bo-Yi Chiang; Chia-Fang Lee (ISCAS, 2006)

Multilevel timing-constrained full-chip routing in hierarchical quad-grid model. - Jin-Tai Yan; Yen-Hsiang Chen; Chia-Fang Lee; Ming-Ching Huang (ISCAS, 2006)

Optimal shielding insertion for inductive noise avoidance. - Jin-Tai Yan; Kuen-Ming Lin; Yen-Hsiang Chen (ISCAS, 2006)

Floorplan-aware decoupling capacitance budgeting on equivalent circuit model. - Jin-Tai Yan; Kai-Ping Lin; Yue-Fong Luo (ISCAS, 2006)

Dynamic Tree Reconstruction with Application to Timing-Constrained Congestion-Driven Global Routing. - Jin-Tai Yan; Chia-Fang Lee; Yen-Hsiang Chen (VLSI Design, 2006)

Routability-Driven Track Routing for Coupling Capacitance Reduction. - Jin-Tai Yan; Zhi-Wei Chen; Kuen-Ming Lin (ICECS, 2007)

Timing-Driven Steiner Tree Construction with Wire Sizing, Buffer Insertion and Obstacle Avoidance. - Jin-Tai Yan; Shi-Qin Huang; Zhi-Wei Chen (ICECS, 2007)

Area-Driven Decoupling Capacitance Allocation in Noise-Aware Floorplan for Signal Integrity. - Jin-Tai Yan; Zhi-Wei Chen; Ming-Yuen Wu (ISCAS, 2007)

Area-driven decoupling capacitance allocation based on space sensitivity analysis for signal integrity. - Jin-Tai Yan; Zhi-Wei Chen; Ming-Yuen Wu (SoCC, 2007)

Timing-Constrained Yield-Driven Wiring Reconstruction for Critical Area Minimization. - Jin-Tai Yan; Bo-Yi Chiang (VLSI Design, 2007)

Timing-driven multi-layer Steiner tree construction with obstacle avoidance. - Jin-Tai Yan; Zhi-Wei Chen (APCCAS, 2008)

Electromigration-aware rectilinear Steiner tree construction for analog circuits. - Jin-Tai Yan; Zhi-Wei Chen (APCCAS, 2008)

Timing-constrained yield-driven redundant via insertion. - Jin-Tai Yan; Zhi-Wei Chen; Bo-Yi Chiang; Yu-Min Lee (APCCAS, 2008)

Flexible escape routing for flip-chip designs. - Jin-Tai Yan; Zhi-Wei Chen (ICECS, 2008)

Simultaneous assignment of power pads and wires for reliability-driven hierarchical power quad-grids. - Jin-Tai Yan; Zhi-Wei Chen (ICECS, 2008)

Thermal-driven white space redistribution for block-level floorplans. - Jin-Tai Yan; Zhi-Wei Chen; Yi-Hsiang Chou; Shun-Hua Lin; Herming Chiueh (ICECS, 2008)

Timing-driven octilinear Steiner tree construction based on Steiner-point reassignment and path reconstruction. - Jin-Tai Yan (ACM Trans. Design Autom. Electr. Syst., 2008)

IO connection assignment and RDL routing for flip-chip designs. - Jin-Tai Yan; Zhi-Wei Chen (ASP-DAC, 2009)

RDL pre-assignment routing for flip-chip designs. - Jin-Tai Yan; Zhi-Wei Chen (ACM Great Lakes Symposium on VLSI, 2009)

Redundant wire insertion for yield improvement. - Jin-Tai Yan; Zhi-Wei Chen (ACM Great Lakes Symposium on VLSI, 2009)

Accurate Transformation-based Timing Analysis for RC Non-tree Circuits. - Zhi-Wei Chen; Jin-Tai Yan; Hsing-Lin Ko (ISCAS, 2009)

Low-power multiplier design with row and column bypassing. - Jin-Tai Yan; Zhi-Wei Chen (SoCC, 2009)

Routability-driven partitioning-based IO assignment for flip-chip designs. - Jin-Tai Yan; Kai-Ping Lu; Zhi-Wei Chen (APCCAS, 2010)

Obstacle-aware longest path using rectangular pattern detouring in routing grids. - Jin-Tai Yan; Ming-Ching Jhong; Zhi-Wei Chen (ASP-DAC, 2010)

Two-sided single-detour untangling for bus routing. - Jin-Tai Yan; Zhi-Wei Chen (DAC, 2010)

Resource-constrained timing-driven link insertion for critical delay reduction. - Jin-Tai Yan; Zhi-Wei Chen (ACM Great Lakes Symposium on VLSI, 2010)

Ordered escape routing via routability-driven pin assignment. - Jin-Tai Yan; Chung-Wei Ke; Zhi-Wei Chen (ACM Great Lakes Symposium on VLSI, 2010)

Routability-driven flip-flop merging process for clock power reduction. - Zhi-Wei Chen; Jin-Tai Yan (ICCD, 2010)

Width-constrained wire sizing for non-tree interconnections. - Zhi-Wei Chen; Jin-Tai Yan (ISCAS, 2010)

Low-cost low-power bypassing-based multiplier design. - Jin-Tai Yan; Zhi-Wei Chen (ISCAS, 2010)

Routability-driven RDL routing with pin reassignment. - Jin-Tai Yan; Ke-Chyuan Chen; Zhi-Wei Chen (SoCC, 2010)

Thermal via planning for temperature reduction in 3D ICs. - Jin-Tai Yan; Yu-Cheng Chang; Zhi-Wei Chen (SoCC, 2010)

Timing-constrained I/O buffer placement for flip-chip designs. - Zhi-Wei Chen; Jin-Tai Yan (DATE, 2011)

Obstacle-aware multiple-source rectilinear Steiner tree with electromigration and IR-drop avoidance. - Jin-Tai Yan; Zhi-Wei Chen (DATE, 2011)

Pre-assignment RDL routing via extraction of maximal net sequence. - Jin-Tai Yan; Zhi-Wei Chen (ICCD, 2011)

Obstacle-aware length-matching bus routing. - Jin-Tai Yan; Zhi-Wei Chen (ISPD, 2011)

Simultaneous escape routing based on routability-driven net ordering. - Jin-Tai Yan; Tung-Yen Sung; Zhi-Wei Chen (SoCC, 2011)

IO connection assignment and RDL routing for flip-chip designs. - Jin-Tai Yan (ACM Trans. Design Autom. Electr. Syst., 2011)

Density-reduction-oriented layer assignment for rectangle escape routing. - Jin-Tai Yan; Jun-Min Chung; Zhi-Wei Chen (ACM Great Lakes Symposium on VLSI, 2012)

Top-down-based symmetrical buffered clock routing. - Jin-Tai Yan; Ming-Chien Huang; Zhi-Wei Chen (ACM Great Lakes Symposium on VLSI, 2012)

Post-layout OPE-predicted redundant wire insertion for clock skew minimization. - Jin-Tai Yan; Zhi-Wei Chen (ICCD, 2012)

Utilization of multi-bit flip-flops for clock power reduction. - Zhi-Wei Chen; Jin-Tai Yan (ICECS, 2012)

Efficient assignment of inter-die signals for die-stacking SiP design. - Jin-Tai Yan; Chia-Han Kao; Ming-Chien Huang; Zhi-Wei Chen (ISCAS, 2012)

Direction-constrained layer assignment for rectangle escape routing. - Jin-Tai Yan; Zhi-Wei Chen (SoCC, 2012)

Resource-constrained link insertion for delay reduction. - Jin-Tai Yan (Integr., 2012)

New optimal layer assignment for bus-oriented escape routing. - Jin-Tai Yan; Zhi-Wei Chen (Integr., 2012)

Timing-constrained replacement using spare cells for design changes. - Zhi-Wei Chen; Jin-Tai Yan (ACM Great Lakes Symposium on VLSI, 2013)

Assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs. - Jin-Tai Yan; Zhi-Wei Chen (ACM Great Lakes Symposium on VLSI, 2013)

Post-layout redundant wire insertion for fixing min-delay violations. - Jin-Tai Yan; Zhi-Wei Chen (ISCAS, 2013)

Routability-constrained multi-bit flip-flop construction for clock power reduction. - Zhi-Wei Chen; Jin-Tai Yan (Integr., 2013)

Efficient micro-bump assignment for RDL routing in 3DICs. - Jin-Tai Yan; Yu-Jen Tseng; Chia-Heng Yen (ICECS, 2014)

Feasible region assignment of routing nets in single-layer routing. - Jin-Tai Yan; Yu-Jen Tseng; Chia-Heng Yen (ISCAS, 2014)

Fault-tolerant analysis of TMR design with noise-aware logic. - Jin-Tai Yan (Integr., 2014)

Length-constrained escape routing of differential pairs. - Jin-Tai Yan (Integr., 2015)

Assignment of inter-die signals in a simplified wiring model for die-stacking SiP designs. - Jin-Tai Yan (Integr., 2015)

Single-layer obstacle-aware routing for substrate interconnections. - Jin-Tai Yan (Integr., 2015)

Cell-aware MBFF utilization for clock power reduction. - Jin-Tai Yan; Meng-Tian Chen; Chia-Heng Yen (ICECS, 2016)

Efficient Layer Assignment of Bus-Oriented Nets in High-Speed PCB Designs. - Jin-Tai Yan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Performance-Driven Assignment of Buffered I/O Signals in Area-I/O Flip-Chip Designs. - Jin-Tai Yan (ACM Trans. Design Autom. Electr. Syst., 2016)

One-Sided Net Untangling With Internal Detours for Bus Routing. - Jin-Tai Yan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Layer Assignment of Escape Buses with Consecutive Constraints in PCB Designs. - Jin-Tai Yan (ACM Trans. Design Autom. Electr. Syst., 2017)

Feasible Assignment of Micro-Bumps in 3D ICs. - Jin-Tai Yan; Chia-Heng Yen (NEWCAS, 2018)

On-Chip Optical Channel Routing for Signal Loss Minimization. - Jin-Tai Yan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Direction-Constrained Rectangle Escape Routing. - Jin-Tai Yan (ACM Trans. Design Autom. Electr. Syst., 2018)

Construction of Delay-Driven GNR Routing Tree. - Jin-Tai Yan; Chia-Heng Yen (NEWCAS, 2019)

Layer Assignment of Buses and Nets With Via-Count Constraint in High-Speed PCB Designs. - Jin-Tai Yan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Single-Layer GNR Routing for Minimization of Bending Delay. - Jin-Tai Yan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Two-sided Net Untangling with Internal Detours for Single-layer Bus Routing. - Jin-Tai Yan (ACM Trans. Design Autom. Electr. Syst., 2019)

Construction of Obstacle-Avoiding Delay-Driven GNR Routing Tree. - Jin-Tai Yan; Po-Yuan Huang; Chien-Yi Wang (TENCON, 2020)

Single-Layer Obstacle-Aware Substrate Routing via Iterative Pin Reassignment and Wire Assignment. - Jin-Tai Yan (ACM Trans. Design Autom. Electr. Syst., 2020)

Single-Layer Delay-Driven GNR Nontree Routing Under Resource Constraint for Yield Improvement. - Jin-Tai Yan (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Delay-Constrained GNR Routing for Layer Minimization. - Jin-Tai Yan (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Efficient Standard-Cell Legalization for Minimization of Total Movement. - Jin-Tai Yan; Po-Yuan Huang; Chia-Hsun Yen (ICECS, 2021)

Length-Matching-Constrained Region Routing in Rapid Single-Flux-Quantum Circuits. - Jin-Tai Yan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Fuzzy-Clustering-Based Circular Topological Via Minimization in PCB Designs. - Jin-Tai Yan (IEEE Trans. Fuzzy Syst., 2021)

Via-Minimization-Oriented Region Routing Under Length-Matching Constraints in Rapid Single-Flux-Quantum Circuits. - Jin-Tai Yan (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Via-Avoidance-Oriented Interposer Routing for Layer Minimization in 2.5-D IC Designs. - Jin-Tai Yan (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Tree-Based Clock Distribution of Multiple-Stage Pipelined Architecture in Rapid Single-Flux-Quantum Circuits. - Jin-Tai Yan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Bus Assignment Considering Flexible Escape Routing for Layer Minimization in PCB Designs. - Jin-Tai Yan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Fixed-Order Placement of Pipelined Architecture in Rapid Single-Flux-Quantum Circuits. - Jin-Tai Yan (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Layer-Minimization-Oriented GNR Area Routing. - Chia-Heng Yen; Jin-Tai Yan (ICECS, 2023)

Design and analysis of sum-prediction adder. - Chia-Heng Yen; Jin-Tai Yan (Integr., 2024)

Delay-Constrained GNR Routing With CNT-Via Insertion in Nano-Scale Designs. - Jin-Tai Yan (IEEE J. Emerg. Sel. Topics Circuits Syst., 2024)