Compact Active Quenching Circuit for Single Photon Avalanche Diodes Arrays. - Lixia Zheng; Huan Hu; Ziqing Weng; Qun Yao; Jin Wu 004; Weifeng Sun (J. Circuits Syst. Comput., 2017)

A hybrid time-to-digital converter based on residual time extraction and amplification. - Jin Wu 004; Wenlong Zhang; Xiangrong Yu; Qi Jiang; Lixia Zheng; Weifeng Sun (Microelectron. J., 2017)

Implementation of a High-Precision and Wide-Range Time-to-Digital Converter With Three-Level Conversion Scheme. - Jin Wu 004; Qi Jiang; Ke Song; Lixia Zheng; Dongchen Sun; Weifeng Sun (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Low-jitter DLL applied for two-segment TDC. - Jin Wu 004; Youzhi Zhang 003; Rongqi Zhao; Kunpeng Zhang; Lixia Zheng; Weifeng Sun (IET Circuits Devices Syst., 2018)

Review: Static and Dynamic Analysis Methods for Multi-Branch Biasing Circuits. - Jin Wu 004; Pengfei Dai; Jie Peng; Lixia Zheng; Weifeng Sun (J. Circuits Syst. Comput., 2018)

64 × 64 GM-APD array-based readout integrated circuit for 3D imaging applications. - Jin Wu 004; Zhiming Qian; Yang Zhao; Xiangrong Yu; Lixia Zheng; Weifeng Sun (Sci. China Inf. Sci., 2019)

A Wide Dynamic Range and Low Bit Error Pixel TDC Suitable for Array Application. - Jin Wu 004; Pengbo Zhang; Shufang Shi; Lixia Zheng; Weifeng Sun (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A low jitter multiplying delay-locked loop with static phase offset elimination applied to time-to-digital converter. - Jin Wu 004; Shuang Chen; Kang Hu; Lixia Zheng; Weifeng Sun (Microelectron. J., 2020)

Modeling and Analysis of a Frequency-Locked Loop Based on Two-Stage Ring Voltage-Controlled Oscillator. - Jin Wu 004; Xingsheng Sun; Mouzhao Zhou; Yue Rong; Lixia Zheng; Weifeng Sun (Circuits Syst. Signal Process., 2021)

A 0.8-3.2 GHz PLL with wide frequency division ratio range. - Jin Wu 004; Jinwen Li; Xudong Wu; Chenggong Wan; Lixia Zheng; Weifeng Sun (Microelectron. J., 2022)

High-Precision Time Interval Measurement Method Based on Sliding Scaled Time-to-Digital Conversion Circuit. - Jin Wu 004; Ruiming Zhong; Yuanfeng Sui; Yang Zhao; Chenggong Wan; Lixia Zheng (IEEE Trans. Instrum. Meas., 2022)

A Region of Interest Technique for Event Driven Typed SPAD Readout Circuit. - Minwei Hu; Jin Wu 004; Chenggong Wan; Lixia Zheng (ASICON, 2023)

A 64×64 active and passive imaging readout circuit based on HgCdTe-LMAPD. - Rixian Tang; Lixia Zheng; Ruiming Zhong; Jin Wu 004 (ASICON, 2023)

A SPAD Relative Address Coding for Lateral Resolution Improvement in Coincidence Detection. - Chenggong Wan; Lixia Zheng; Jin Wu 004 (ASICON, 2023)

A low jitter fractional PLL with offset current charge pump. - Jin Wu 004; Minwei Hu; Xudong Wu; Yang Zuo; Chenggong Wan; Lixia Zheng; Weifeng Sun (Microelectron. J., 2023)

A Low-Power Capacitorless LDO Regulator with Transient Enhancement Structure. - Lixia Zheng; Yi Zhu; Huiyong Xian; Jinwen Li; Chenggong Wan; Jin Wu 004; Weifeng Sun (J. Circuits Syst. Comput., 2024)

High-Precision GRO-Based ROIC Adopting Sliding Scale Average Method for SPAD Array. - Lixia Zheng; Yanna Zheng; Chenggong Wan; Xuyan Li; Weifeng Sun; Jin Wu 004 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A broadband low-noise VCO circuit based on a hybrid analog-digital control loop. - Lixia Zheng; Yuxiao Li; Zilu Zhao; Hehe Tian; Jin Wu 004; Weifeng Sun (Integr., 2025)

A SPAD Image Sensor With Main-Sub-TDC-Based Coincidence Detection. - Chenggong Wan; Yi Zhu; Yingjie Ma; Xue Li; Lixia Zheng; Jin Wu 004; Weifeng Sun (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)