Lazy symbolic model checking. - Jin Yang 006; Andreas Tiemeyer (DAC, 2000)

Generalized Symbolic Trajectory Evaluation - Abstraction in Action. - Jin Yang 006; Carl-Johan H. Seger (FMCAD, 2002)

GSTE through a case study. - Jin Yang 006; Amit Goel (ICCAD, 2002)

Reasoning about GSTE Assertion Graphs. - Alan J. Hu; Jeremy Casas; Jin Yang 006 (CHARME, 2003)

Introduction to generalized symbolic trajectory evaluation. - Jin Yang 006; Carl-Johan H. Seger (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Compositional Specification and Model Checking in GSTE. - Jin Yang 006; Carl-Johan H. Seger (CAV, 2004)

Quantum logic synthesis by symbolic reachability analysis. - William N. N. Hung; Xiaoyu Song; Guowu Yang; Jin Yang 006; Marek A. Perkowski (DAC, 2004)

Partitioned model checking from software specifications. - Xiushan Feng; Alan J. Hu; Jin Yang 006 (ASP-DAC, 2005)

Tightly integrate dynamic verification with formal verification: a GSTE based approach. - Jin Yang 006; Avi Puder (ASP-DAC, 2005)

Implication of assertion graphs in GSTE. - Guowu Yang; Jin Yang 006; William N. N. Hung; Xiaoyu Song (ASP-DAC, 2005)

Verification Challenges and Opportunities in the New Era of Microprocessor Design. - Jin Yang 006 (ATVA, 2006)

Maximal Models of Assertion Graph in GSTE. - Guowu Yang; Jin Yang 006; Xiaoyu Song; Fei Xie 004 (TAMC, 2006)

Optimal synthesis of multiple output Boolean functions using a set of quantum gates by symbolic reachability analysis. - William N. N. Hung; Xiaoyu Song; Guowu Yang; Jin Yang 006; Marek A. Perkowski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Automatic Abstraction Refinement for Generalized Symbolic Trajectory Evaluation. - Yan Chen 001; Yujing He; Fei Xie 004; Jin Yang 006 (FMCAD, 2007)

Optimizing automatic abstraction refinement for generalized symbolic trajectory evaluation. - Yan Chen 001; Fei Xie 004; Jin Yang 006 (DAC, 2008)

BackSpace: Formal Analysis for Post-Silicon Debug. - Flavio M. de Paula; Marcel Gort; Alan J. Hu; Steven J. E. Wilton; Jin Yang 006 (FMCAD, 2008)

Formal Verification for High-Assurance Behavioral Synthesis. - Sandip Ray; Kecheng Hao; Yan Chen 001; Fei Xie 004; Jin Yang 006 (ATVA, 2009)

Optimizing equivalence checking for behavioral synthesis. - Kecheng Hao; Fei Xie 004; Sandip Ray; Jin Yang 006 (DATE, 2010)

SystemVerilog Assertions: Past, Present, and Future SVA Standardization Experience. - Doron Bustan; Dmitry Korchemny; Erik Seligman; Jin Yang 006 (IEEE Des. Test Comput., 2012)

Formal-Analysis-Based Trace Computation for Post-Silicon Debug. - Marcel Gort; Flavio M. de Paula; Johnny J. W. Kuan; Tor M. Aamodt; Alan J. Hu; Steven J. E. Wilton; Jin Yang 006 (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Security of SoC firmware load protocols. - Sava Krstic; Jin Yang 006; David W. Palmer; Randy B. Osborne; Eran Talmor (HOST, 2014)

From visual to logical formalisms for SoC validation. - Ranan Fraer; Doron Keren; Zurab Khasidashvili; Alexander Novakovsky; Avi Puder; Eli Singerman; Eran Talmor; Moshe Y. Vardi; Jin Yang 006 (MEMOCODE, 2014)

Correctness and security at odds: post-silicon validation of modern SoC designs. - Sandip Ray; Jin Yang 006; Abhishek Basak; Swarup Bhunia (DAC, 2015)

Protocol-guided analysis of post-silicon traces under limited observability. - Hao Zheng 001; Yuting Cao; Sandip Ray; Jin Yang 006 (ISQED, 2016)

A Post-Silicon Trace Analysis Approach for System-on-Chip Protocol Debug. - Yuting Cao; Hao Zheng 001; Hernan M. Palombo; Sandip Ray; Jin Yang 006 (ICCD, 2017)

UEFI Firmware Fuzzing with Simics Virtual Platform. - Zhenkun Yang; Yuriy Viktorov; Jin Yang 006; Jiewen Yao; Vincent Zimmer (DAC, 2020)

Mining Message Flows using Recurrent Neural Networks for System-on-Chip Designs. - Yuting Cao; Parijat Mukherjee; Mahesh Ketkar; Jin Yang 006; Hao Zheng 001 (ISQED, 2020)

A Post-Silicon Trace Analysis Approach for System-on-Chip Protocol Debug. - Yuting Cao; Hao Zheng 001; Sandip Ray; Jin Yang 006 (CoRR, 2020)

Model Synthesis for Communication Traces of System Designs. - Hao Zheng 001; Md Rubel Ahmed; Parijat Mukherjee; Mahesh C. Ketkar; Jin Yang 006 (ICCD, 2021)

Mining Message Flows from System-on-Chip Execution Traces. - Md Rubel Ahmed; Hao Zheng 001; Parijat Mukherjee; Mahesh C. Ketkar; Jin Yang 006 (ISQED, 2021)

A Comparative Study of Specification Mining Methods for SoC Communication Traces. - Md Rubel Ahmed; Hao Zheng 001; Parijat Mukherjee; Mahesh C. Ketkar; Jin Yang 006 (ISVLSI, 2021)

Model Synthesis for Communication Traces of System-on-Chip Designs. - Hao Zheng 001; Md Rubel Ahmed; Parijat Mukherjee; Mahesh C. Ketkar; Jin Yang 006 (CoRR, 2021)

A Highly Configurable Hardware/Software Stack for DNN Inference Acceleration. - Suvadeep Banerjee; Steve Burns 002; Pasquale Cocchini; Abhijit Davare; Shweta Jain 005; Desmond Kirkpatrick; Anton Sorokin; Jin Yang 006; Zhenkun Yang (CoRR, 2021)

A Hertzian contact based model to estimate thermal resistance of thermal interface material for high-performance microprocessors. - David Shia; Jin Yang 006 (Microelectron. J., 2021)

Accelerator design with decoupled hardware customizations: benefits and challenges: invited. - Debjit Pal; Yi-Hsiang Lai; Shaojie Xiang; Niansong Zhang; Hongzheng Chen; Jeremy Casas; Pasquale Cocchini; Zhenkun Yang; Jin Yang 006; Louis-Noël Pouchet; Zhiru Zhang (DAC, 2022)

Mining Patterns From Concurrent Execution Traces. - Md Rubel Ahmed; Hao Zheng 001; Parijat Mukherjee; Mahesh C. Ketkar; Jin Yang 006 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

An Equivalence Checking Framework for Agile Hardware Design. - Yanzhao Wang; Fei Xie 004; Zhenkun Yang; Pasquale Cocchini; Jin Yang 006 (ASP-DAC, 2023)

Towards A Formally Verified Fully Homomorphic Encryption Compute Engine. - Jeremy Casas; Zhenkun Yang; Wen Wang; Jin Yang 006; Adwait Godbole (DAC, 2023)

Invited: A Scalable Formal Approach for Correctness-Assured Hardware Design. - Jin Yang 006; Jeremy Casas; Zhenkun Yang (DAC, 2023)

An Automated Verification Framework for HalideIR-Based Compiler Transformations. - Yanzhao Wang; Fei Xie 004; Zhenkun Yang; Jeremy Casas; Pasquale Cocchini; Jin Yang 006 (DATE, 2023)

High-level Synthesis for Domain Specific Computing. - Hanchen Ye; HyeGang Jun; Jin Yang 006; Deming Chen (ISPD, 2023)

Towards A Correct-by-Construction FHE Model. - Zhenkun Yang; Wen Wang; Jeremy Casas; Pasquale Cocchini; Jin Yang 006 (IACR Cryptol. ePrint Arch., 2023)

Correct-by-Construction Design of Custom Accelerator Microarchitectures. - Jin Yang 006; Zhenkun Yang; Jeremy Casas; Sandip Ray (IEEE Trans. Computers, 2024)

A Systematic Translation Validation Framework for MLIR-Based Compilers. - Yanzhao Wang; Fei Xie 004; Zhenkun Yang; Pasquale Cocchini; Jin Yang 006 (Int. J. Softw. Eng. Knowl. Eng., 2024)

Formal Verification of a Custom Compiler for a Fully Homomorphic Encryption Accelerator. - Zhenkun Yang; Suvadeep Banerjee; Jeremy Casas; Jin Yang 006 (ISQED, 2025)