Implement 32-bit RISC-V Architecture Processor using Verilog HDL. - Jin-Yang Lai; Chiung-An Chen; Shih-Lun Chen; Chun-Yu Su (ISPACS, 2021)

USB 3.0 Using FPGA Optimization for 8b/10b Encoder/Decoder. - Chun-Yu Su; Chiung-An Chen; Shih-Lun Chen; Jin-Yang Lai (ISPACS, 2021)