25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector. - Hyun-Woo Lee; Junyoung Song; Sangah Hyun; Seunggeun Baek; Yuri Lim; Jungwan Lee; Minsu Park; Haerang Choi; Changkyu Choi; Jin-Youp Cha; Jaeil Kim; Hoon Choi; et al. (ISSCC, 2014)

A 16Gb/s/pin 8Gb GDDR6 DRAM with bandwidth extension techniques for high-speed applications. - Kyu-Dong Hwang; Boram Kim; Sang-Yeon Byeon; Kyu-Young Kim; Dae-Han Kwon; Hyun-Bae Lee; Geun-Il Lee; Sang-Sic Yoon; Jin-Youp Cha; Soo-Young Jang; Seung-Hun Lee; Yongsuk Joo; et al. (ISSCC, 2018)

13.1 A 35.4Gb/s/pin 16Gb GDDR7 with a Low-Power Clocking Architecture and PAM3 IO Circuitry. - Jaehyeok Yang; Hyeongjun Ko; Kyunghoon Kim; Hyunsu Park; Jihwan Park; Ji-Hyo Kang; Jin-Youp Cha; Seongjin Kim; Youngtaek Kim; Minsoo Park; Gangsik Lee; Keonho Lee; et al. (ISSCC, 2024)

22.3 A 42Gb/s Single-Ended Hybrid-DFE PAM-3 Receiver for GDDR7 Memory Interfaces. - Boram Kim; Hankyu Chi; Hyeongjun Ko; Sang-Yeon Byeon; Sungkwon Lee; Changhyun Pyo; Seulgi Kim; Byungjun Kang; Eunji Song; Kwangjin Na; Jin-Youp Cha; Hyesoo Kim; et al. (ISSCC, 2025)