An 11-bit 100-MS/s Pipelined-SAR ADC Reusing PVT-Stabilized Dynamic Comparator in 65-nm CMOS. - Jin Zhang 034; Xiaoqian Ren; Shubin Liu; Chi-Hang Chan; Zhangming Zhu (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A 79.1dB-SNDR 20MHz-BW 2nd-Order SAR-Assisted Noise-Shaping Pipeline ADC with Gain and Offset Background Calibrations Based on Convergence Enhanced Split-Over-Time Architecture. - Yanbo Zhang; Jin Zhang 034; Shubin Liu; Zhangming Zhu; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (CICC, 2021)

A 20 MHz Bandwidth 79 dB SNDR SAR-Assisted Noise-Shaping Pipeline ADC With Gain and Offset Calibrations. - Yanbo Zhang; Jin Zhang 034; Shubin Liu; Ruixue Ding; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (IEEE J. Solid State Circuits, 2022)

A 14b 180MS/s Pipeline-SAR ADC With Adaptive-Region-Selection Technique and Gain Error Calibration. - Junyan Hao; Yi Shen 007; Jin Zhang 034; Yanbo Zhang; Shubin Liu; Zhangming Zhu (IEEE Trans. Circuits Syst. II Express Briefs, 2024)