A two-stage slicer employing body biasing for 64-Gb/s PAM4 wireline receiver in 22-nm FDSOI technology. - Ai He; Binhong Li; Jianzhong Li; Xing Zhao; Jincai Guo; Jianping Wang; Xiangqian Zeng; Yun Wang; Tianchun Ye 001; Quan Xue (Microelectron. J., 2024)