Improving Reliability of Deduplication-Based Storage Systems with Per-File Parity. - Suzhen Wu; Huagao Luan; Bo Mao; Hong Jiang 001; Gen Niu; Hui Rao; Fang Yu; Jindong Zhou (SRDS, 2018)

Improving Flash Memory Performance and Reliability for Smartphones With I/O Deduplication. - Bo Mao; Jindong Zhou; Suzhen Wu; Hong Jiang 001; Xiao Chen; Weijian Yang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

PFP: Improving the Reliability of Deduplication-based Storage Systems with Per-File Parity. - Suzhen Wu; Bo Mao; Hong Jiang 001; Huagao Luan; Jindong Zhou (IEEE Trans. Parallel Distributed Syst., 2019)

EaD: a Collision-free and High Performance Deduplication Scheme for Flash Storage Systems. - Suzhen Wu; Jindong Zhou; Weidong Zhu 002; Hong Jiang 001; Zhijie Huang; Zhirong Shen; Bo Mao (ICCD, 2020)

ICARUS: A Lightweight Neural Plenoptic Rendering Architecture. - Chaolin Rao; Huangjie Yu; Haochuan Wan; Jindong Zhou; Yueyang Zheng; Yu Ma; Anpei Chen; Minye Wu; Binzhe Yuan; Pingqiang Zhou; Xin Lou; Jingyi Yu (CoRR, 2022)

ICARUS: A Specialized Architecture for Neural Radiance Fields Rendering. - Chaolin Rao; Huangjie Yu; Haochuan Wan; Jindong Zhou; Yueyang Zheng; Minye Wu; Yu Ma; Anpei Chen; Binzhe Yuan; Pingqiang Zhou; Xin Lou; Jingyi Yu (ACM Trans. Graph., 2022)

Exploring Remote Power Attacks Targeting Parallel Data Encryption On Multi-Tenant FPGAs. - Yankun Zhu; Jindong Zhou; Pingqiang Zhou (ACM Great Lakes Symposium on VLSI, 2023)

The study of TSV-induced and strained silicon-enhanced stress in 3D-ICs. - Jindong Zhou; Yuyang Chen; Youliang Jing; Pingqiang Zhou (Integr., 2023)

EaD: ECC-Assisted Deduplication With High Performance and Low Memory Overhead for Ultra-Low Latency Flash Storage. - Suzhen Wu; Chunfeng Du; Weidong Zhu 002; Jindong Zhou; Hong Jiang 001; Bo Mao; Lingfang Zeng (IEEE Trans. Computers, 2023)

Spiking-NeRF: Spiking Neural Network for Energy-Efficient Neural Rendering. - Ziwen Li; Yu Ma; Jindong Zhou; Pingqiang Zhou (ACM J. Emerg. Technol. Comput. Syst., 2024)

Clock-Wirelength-Driven Detailed Placement. - Ziang Ge; Yikai Liu; Jindong Zhou; Pingqiang Zhou (ACM Great Lakes Symposium on VLSI, 2025)

Inductance-aware Clock Network Synthesis Considering Hierarchical Interconnects in 3D ICs. - Jindong Zhou; Ziang Ge; Chenbo Xi; Pingqiang Zhou (ACM Great Lakes Symposium on VLSI, 2025)