Gate-level timing verification using waveform narrowing. - Jindrich Zejda; Eduard Cerny (EURO-DAC, 1994)

Bounding Switching Activity in CMOS Circuits Using Constraint Resolution. - Jindrich Zejda; Eduard Cerny; S. Shenoy; Nicholas C. Rumin (ED&TC, 1996)

General framework for removal of clock network pessimism. - Jindrich Zejda; Paul Frain (ICCAD, 2002)

Analytical modeling of crosstalk noise waveforms using Weibull function. - Alireza Kasnavi; Joddy W. Wang; Mahmoud Shahram; Jindrich Zejda (ICCAD, 2004)

Noise Library Characterization for Large Capacity Static Noise Analysis Tools. - Alex Gyure; Alireza Kasnavi; Sam C. Lo; Peivand F. Tehrani; William Shu; Mahmoud Shahram; Joddy W. Wang; Jindrich Zejda (ISQED, 2005)

TBNM - Transistor-Level Boundary Model for Fast Gate-Level Noise Analysis of Macro Blocks. - Jindrich Zejda; Li Ding 002 (ISQED, 2006)

Fundamentals of timing information for test: How simple can we get? - Rohit Kapur; Jindrich Zejda; Thomas W. Williams (ITC, 2007)