Novel Mixed Codes for Multiple-Cell Upsets Mitigation in Static RAMs. - Jing Guo 004; Liyi Xiao; Zhigang Mao; Qiang Zhao (IEEE Micro, 2013)

Novel Low-Power and Highly Reliable Radiation Hardened Memory Cell for 65 nm CMOS Technology. - Jing Guo 004; Liyi Xiao; Zhigang Mao (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code. - Jing Guo 004; Liyi Xiao; Zhigang Mao; Qiang Zhao (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Fault Secure Encoder and Decoder Designs for Matrix Codes. - Shanshan Liu 001; Liyi Xiao; Jing Guo 004; Zhigang Mao (CAD/Graphics, 2015)

Hardened design based on advanced orthogonal Latin code against two adjacent multiple bit upsets (MBUs) in memories. - Liyi Xiao; Jiaqiang Li; Jie Li 030; Jing Guo 004 (ISQED, 2015)

Low cost and highly reliable radiation hardened latch design in 65 nm CMOS technology. - Chunhua Qi; Liyi Xiao; Jing Guo 004; Tianqi Wang (Microelectron. Reliab., 2015)

Soft Error Hardened Memory Design for Nanoscale Complementary Metal Oxide Semiconductor Technology. - Jing Guo 004; Liyi Xiao; Tianqi Wang; Shanshan Liu 001; Xu Wang; Zhigang Mao (IEEE Trans. Reliab., 2015)

A Cost-Effective Relative Humidity Sensor Based on Side Coupling Induction Technology. - Yingzi Zhang; Yulong Hou; Wenyi Liu; Huixin Zhang; Yanjun Zhang; Zhidong Zhang; Jing Guo 004; Jia Liu 006; Liang Zhang 016; Qiu-lin Tan (Sensors, 2017)

Novel Radiation-Hardened-by-Design (RHBD) 12T Memory Cell for Aerospace Applications in Nanoscale CMOS Technology. - Jing Guo 004; Lei Zhu 004; Wenyi Liu; Hai Huang; Shanshan Liu 001; Tianqi Wang; Liyi Xiao; Zhigang Mao (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Radiation Hardening by Design of a Novel Double-Node-Upset-Tolerant Latch Combined with Layout Technique. - Aibin Yan; Zhile Chen; Zhengfeng Huang; Xiangsheng Fang; Maoxiang Yi; Jing Guo 004 (ITC-Asia, 2018)

Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications. - Jing Guo 004; Lei Zhu 004; Yu Sun; Huiliang Cao; Hai Huang; Tianqi Wang; Chunhua Qi; Rongsheng Zhang; Xuebing Cao; Liyi Xiao; Zhigang Mao (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Novel Double-Node-Upset-Tolerant Memory Cell Designs Through Radiation-Hardening-by-Design and Layout. - Aibin Yan; Zhen Wu; Jing Guo 004; Jie Song; Xiaoqing Wen (IEEE Trans. Reliab., 2019)

A CMOS Majority Logic Gate and its Application to One-Step ML Decodable Codes. - Jing Guo 004; Shanshan Liu 001; Lei Zhu 004; Fabrizio Lombardi (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Self-Recovery Tolerance Latch Design Based on the Radiation Mechanism. - Qiang Li; Xiaohui Su; Jing Guo 004; Chunhua Qi (IEEE Access, 2020)

Design of Robust Latch for Multiple-Node Upset (MNU) Mitigation in Nanoscale CMOS Technology. - Nan Zhang; Xiaohui Su; Jing Guo 004 (IEEE Access, 2020)

Design and Evaluation of Low-Complexity Radiation Hardened CMOS Latch for Double-Node Upset Tolerance. - Jing Guo 004; Shanshan Liu 001; Lei Zhu 004; Fabrizio Lombardi (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

High-Performance CMOS Latch Designs for Recovering All Single and Double Node Upsets. - Jing Guo 004; Shanshan Liu 001; Xiaohui Su; Chunhua Qi; Fabrizio Lombardi (IEEE Trans. Aerosp. Electron. Syst., 2021)

Exploiting Asymmetry in eDRAM Errors for Redundancy-Free Error-Tolerant Design. - Shanshan Liu 001; Pedro Reviriego; Jing Guo 004; Jie Han 001; Fabrizio Lombardi (IEEE Trans. Emerg. Top. Comput., 2021)

Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS. - Aibin Yan; Chaoping Lai; Yinlei Zhang; Jie Cui 004; Zhengfeng Huang; Jie Song; Jing Guo 004; Xiaoqing Wen (IEEE Trans. Emerg. Top. Comput., 2021)

A Polarity-Driven Radiation-Hardened Latch design for Single Event Upset Tolerance. - Shanshan Liu 001; Jing Guo 004; Xiaochen Tang; Pedro Reviriego; Fabrizio Lombardi (DFT, 2022)