LAEPS: LDPC LLR Adaptive Estimation Based on Pattern Set Distribution Variation in 3D Charge Trap NAND Flash Memories. - Qianhui Li; Yiyang Jiang; Qi Wang 041; Liu Yang; Zexia Wang; Xiaolei Yu; Jing He 020; Zongliang Huo (ICTA, 2021)

Efficient Data Recovery Technique for 3D TLC NAND Flash Memory based on WL Interference. - Liu Yang; Qi Wang 041; Qianhui Li; Xiaolei Yu; Jing He 020; Zongliang Huo (IRPS, 2021)

Gradual Channel Estimation Method for TLC NAND Flash Memory. - Liu Yang; Qi Wang 041; Qianhui Li; Xiaolei Yu; Jing He 020; Zongliang Huo (IEEE Embed. Syst. Lett., 2022)

A novel adaptive-refresh scheme to reduce refresh with page endurance variance in 3D TLC NAND flash memories. - Xianliang Wang; Qi Wang 041; Bo Zhang; Jing He 020; Zongliang Huo (IEICE Electron. Express, 2022)

FBEL: Enhanced LLR optimization algorithm based on the VSER prediction by flag bits in the bit-flipping scheme. - Bo Zhang; Qi Wang 041; Xiaolei Yu; Qianhui Li; Jing He 020; Xianliang Wang; Qianqi Zhao; Xuhong Qiang; Zongliang Huo; Tianchun Ye 001 (IEICE Electron. Express, 2023)

LIAD: A Method for Extending the Effective Time of 3-D TLC NAND Flash Hard Decision. - Xiaolei Yu; Jing He 020; Qianhui Li; Bo Zhang; Xianliang Wang; Liu Yang; Tian-Chun Ye 001; Qi Wang 041; Zongliang Huo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Interleaved LDPC Decoding Scheme Improves 3-D TLC NAND Flash Memory System Performance. - Xiaolei Yu; Jing He 020; Bo Zhang; Xianliang Wang; Qianhui Li; Qi Wang 041; Zongliang Huo; Tian-Chun Ye 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

DMMC: A Polar Code Construction Method for Improving Performance in TLC NAND Flash. - Xiaolei Yu; Jing He 020; Qianhui Li; Bo Zhang; Xianliang Wang; Qi Wang 041; Zongliang Huo (IEEE Embed. Syst. Lett., 2024)

NV-APP: Invalid Programming Performance Improved No-Verify and Adaptive Pulse Programming Scheme for 3-D QLC nand Flash. - Qianqi Zhao; Jing He 020; Tong Qu; Wentian Wu; Qianhui Li; Qi Wang 041; Zongliang Huo; Tian-Chun Ye 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)