High Performance and Low Power Electronics on Flexible Substrate. - Jing Li 073; Kunhyuk Kang; Aditya Bansal; Kaushik Roy 001 (DAC, 2007)

Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI. - Yiran Chen 001; Hai Li 001; Jing Li 073; Cheng-Kok Koh (ISLPED, 2007)

A generic and reconfigurable test paradigm using Low-cost integrated Poly-Si TFTs. - Jing Li 073; Swaroop Ghosh; Kaushik Roy 001 (ITC, 2007)

Variation-tolerant Spin-Torque Transfer (STT) MRAM array for yield enhancement. - Jing Li 073; Haixin Liu; Sayeef S. Salahuddin; Kaushik Roy 001 (CICC, 2008)

Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement. - Jing Li 073; Charles Augustine; Sayeef S. Salahuddin; Kaushik Roy 001 (DAC, 2008)

An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs. - Jing Li 073; Aditya Bansal; Swaroop Ghosh; Kaushik Roy 001 (ACM J. Emerg. Technol. Comput. Syst., 2008)

An alternate design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective. - Jing Li 073; Patrick Ndai; Ashish Goel; Haixin Liu; Kaushik Roy 001 (ASP-DAC, 2009)

Variation Estimation and Compensation Technique in Scaled LTPS TFT Circuits for Low-Power Low-Cost Applications. - Jing Li 073; Kunhyuk Kang; Kaushik Roy 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance. - Yiran Chen 001; Hai Li 001; Cheng-Kok Koh; Guangyu Sun 003; Jing Li 073; Yuan Xie 001; Kaushik Roy 001 (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture Perspective. - Jing Li 073; Patrick Ndai; Ashish Goel; Sayeef S. Salahuddin; Kaushik Roy 001 (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Post-silicon calibration of analog CMOS using phase-change memory cells. - Cheng-Yuan Wen; Jeyanandh Paramesh; Larry T. Pileggi; Jing Li 073; SangBum Kim; Jonathan E. Proesel; Chung Lam (ESSCIRC, 2011)

Phase change memory. - Jing Li 073; Chung Lam (Sci. China Inf. Sci., 2011)

A case for small row buffers in non-volatile main memories. - Justin Meza; Jing Li 073; Onur Mutlu (ICCD, 2012)

1 Mb 0.41 µm2 2T-2R Cell Nonvolatile TCAM With Two-Bit Encoding and Clocked Self-Referenced Sensing. - Jing Li 073; Robert K. Montoye; Masatoshi Ishii; Leland Chang (IEEE J. Solid State Circuits, 2014)

Enabling phase-change memory for data-centric computing: Technology, circuitand system. - Jing Li 073 (ISCAS, 2015)

Reconfigurable in-memory computing with resistive memory crossbar. - Yue Zha; Jing Li 073 (ICCAD, 2016)

Accelerating Large-Scale Graph Analytics with FPGA and HMC. - Soroosh Khoram; Jialiang Zhang; Maxwell Strange; Jing Li 073 (FCCM, 2017)

A Mixed-Signal Data-Centric Reconfigurable Architecture enabled by RRAM Technology (Abstract Only). - Yue Zha; Jialiang Zhang; Zhiqiang Wei; Jing Li 073 (FPGA, 2017)

Boosting the Performance of FPGA-based Graph Processor using Hybrid Memory Cube: A Case for Breadth First Search. - Jialiang Zhang; Soroosh Khoram; Jing Li 073 (FPGA, 2017)

RRAM-based reconfigurable in-memory computing architecture with hybrid routing. - Yue Zha; Jing Li 073 (ICCAD, 2017)

Challenges and Opportunities: From Near-memory Computing to In-memory Computing. - Soroosh Khoram; Yue Zha; Jialiang Zhang; Jing Li 073 (ISPD, 2017)

IMEC: A Fully Morphable In-Memory Computing Fabric Enabled by Resistive Crossbar. - Yue Zha; Jing Li 073 (IEEE Comput. Archit. Lett., 2017)

Liquid Silicon-Monona: A Reconfigurable Memory-Oriented Computing Fabric with Scalable Multi-Context Support. - Yue Zha; Jing Li 073 (ASPLOS, 2018)

Efficient Large-Scale Approximate Nearest Neighbor Search on OpenCL FPGA. - Jialiang Zhang; Soroosh Khoram; Jing Li 073 (CVPR, 2018)

PQ-CNN: Accelerating Product Quantized Convolutional Neural Network on FPGA. - Jialiang Zhang; Jing Li 073 (FCCM, 2018)

Accelerating Graph Analytics by Co-Optimizing Storage and Access on an FPGA-HMC Platform. - Soroosh Khoram; Jialiang Zhang; Maxwell Strange; Jing Li 073 (FPGA, 2018)

Liquid Silicon: A Data-Centric Reconfigurable Architecture Enabled by RRAM Technology. - Yue Zha; Jing Li 073 (FPGA, 2018)

Degree-aware Hybrid Graph Traversal on FPGA-HMC Platform. - Jialiang Zhang; Jing Li 073 (FPGA, 2018)

Adaptive Quantization of Neural Networks. - Soroosh Khoram; Jing Li 073 (ICLR (Poster), 2018)

An Alternative Analytical Approach to Associative Processing. - Soroosh Khoram; Yue Zha; Jing Li 073 (IEEE Comput. Archit. Lett., 2018)

CMA: A Reconfigurable Complex Matching Accelerator for Wire-Speed Network Intrusion Detection. - Yue Zha; Jing Li 073 (IEEE Comput. Archit. Lett., 2018)

Evaluating Row Buffer Locality in Future Non-Volatile Main Memories. - Justin Meza; Jing Li 073; Onur Mutlu (CoRR, 2018)

Specialization: A New Path Towards Low Power. - Yue Zha; Jing Li 073 (J. Low Power Electron., 2018)

MEG: A RISCV-Based System Simulation Infrastructure for Exploring Memory Optimization Using FPGAs and Hybrid Memory Cube. - Jialiang Zhang; Yang Liu; Gaurav Jain; Yue Zha; Jonathan Ta; Jing Li 073 (FCCM, 2019)

Unleashing the Power of Soft Logic for Convolutional Neural Network Acceleration via Product Quantization. - Jialiang Zhang; Jing Li 073 (FPGA, 2019)

Liquid Silicon: A Nonvolatile Fully Programmable Processing-In-Memory Processor with Monolithically Integrated ReRAM for Big Data/Machine Learning Applications. - Yue Zha; Etienne Nowak; Jing Li 073 (VLSI Circuits, 2019)

SysML: The New Frontier of Machine Learning Systems. - Alexander Ratner; Dan Alistarh; Gustavo Alonso; David G. Andersen; Peter Bailis; Sarah Bird; Nicholas Carlini; Bryan Catanzaro; Eric S. Chung; Bill Dally; Jeff Dean; Inderjit S. Dhillon; et al. (CoRR, 2019)

Interleaved Composite Quantization for High-Dimensional Similarity Search. - Soroosh Khoram; Stephen J. Wright 001; Jing Li 073 (CoRR, 2019)

TOCO: A Framework for Compressing Neural Network Models Based on Tolerance Analysis. - Soroosh Khoram; Jing Li 073 (CoRR, 2019)

Virtualizing FPGAs in the Cloud. - Yue Zha; Jing Li 073 (ASPLOS, 2020)

Hyper-Ap: Enhancing Associative Processing Through A Full-Stack Optimization. - Yue Zha; Jing Li 073 (ISCA, 2020)

Liquid Silicon: A Nonvolatile Fully Programmable Processing-in-Memory Processor With Monolithically Integrated ReRAM. - Yue Zha; Etienne Nowak; Jing Li 073 (IEEE J. Solid State Circuits, 2020)

MEG: A RISCV-based System Emulation Infrastructure for Near-data Processing Using FPGAs and High-bandwidth Memory. - Jialiang Zhang; Yue Zha; Nicholas Beckwith; Bangya Liu; Jing Li 073 (ACM Trans. Reconfigurable Technol. Syst., 2020)

When application-specific ISA meets FPGAs: a multi-layer virtualization framework for heterogeneous cloud FPGAs. - Yue Zha; Jing Li 073 (ASPLOS, 2021)

GORDON: Benchmarking Optane DC Persistent Memory Modules on FPGAs. - Jialiang Zhang; Nicholas Beckwith; Jing Jane Li (FCCM, 2021)

Hetero-ViTAL: A Virtualization Stack for Heterogeneous FPGA Clusters. - Yue Zha; Jing Li 073 (ISCA, 2021)

Software-defined address mapping: a case on 3D memory. - Jialiang Zhang; Michael M. Swift; Jing Jane Li (ASPLOS, 2022)

Augmenting HLS with Zero-Overhead Application-Specific Address Mapping for Optane DCPMM. - Nicholas Beckwith; Jialiang Zhang; Jing Jane Li (FCCM, 2022)

Revisiting PathFinder Routing Algorithm. - Yue Zha; Jing Li 073 (FPGA, 2022)

DONGLE: Direct FPGA-Orchestrated NVMe Storage for HLS. - Linus Y. Wong; Jialiang Zhang; Jing Jane Li (FPGA, 2023)

Introduction to the Special Section on FCCM 2022. - Jing Li 073; Martin C. Herbordt (ACM Trans. Reconfigurable Technol. Syst., 2023)

LaMAGIC: Language-Model-based Topology Generation for Analog Integrated Circuits. - Chen-Chia Chang; Yikang Shan; Shaoze Fan; Jing Li 073; Shun Zhang; Ningyuan Cao; Yiran Chen 001; Xin Zhang 025 (CoRR, 2024)

DONGLE 2.0: Direct FPGA-Orchestrated NVMe Storage for HLS. - Linus Y. Wong; Jialiang Zhang; Jing Jane Li (ACM Trans. Reconfigurable Technol. Syst., 2024)