Performance sensitivity analysis using statistical method and its applications to delay. - Jing-Jia Liou; Angela Krstic; Kwang-Ting Cheng; Deb Aditya Mukherjee; Sandip Kundu (ASP-DAC, 2000)

Path Selection and Pattern Generation for Dynamic Timing Analysis Considering Power Supply Noise Effects. - Jing-Jia Liou; Angela Krstic; Yi-Min Jiang; Kwang-Ting Cheng (ICCAD, 2000)

Path Selection for Delay Testing of Deep Sub-Micron Devices Using Statistical Performance Sensitivity Analysis. - Jing-Jia Liou; Kwang-Ting Cheng; Deb Aditya Mukherjee (VTS, 2000)

Fast Statistical Timing Analysis By Probabilistic Event Propagation. - Jing-Jia Liou; Kwang-Ting Cheng; Sandip Kundu; Angela Krstic (DAC, 2001)

Delay testing considering crosstalk-induced effects. - Angela Krstic; Jing-Jia Liou; Yi-Min Jiang; Kwang-Ting Cheng (ITC, 2001)

False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation. - Jing-Jia Liou; Angela Krstic; Li-C. Wang; Kwang-Ting Cheng (DAC, 2002)

Enhancing test efficiency for delay fault testing using multiple-clocked schemes. - Jing-Jia Liou; Li-C. Wang; Kwang-Ting Cheng; Jennifer Dworak; M. Ray Mercer; Rohit Kapur; Thomas W. Williams (DAC, 2002)

On theoretical and practical considerations of path selection for delay fault testing. - Jing-Jia Liou; Li-C. Wang; Kwang-Ting Cheng (ICCAD, 2002)

Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme. - Jing-Jia Liou; Li-C. Wang; Kwang-Ting Cheng; Jennifer Dworak; M. Ray Mercer; Rohit Kapur; Thomas W. Williams (ITC, 2002)

Experience in critical path selection for deep sub-micron delay test and timing validation. - Jing-Jia Liou; Li-C. Wang; Angela Krstic; Kwang-Ting Cheng (ASP-DAC, 2003)

Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models. - Angela Krstic; Li-C. Wang; Kwang-Ting Cheng; Jing-Jia Liou; T. M. Mak (DAC, 2003)

Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step. - Angela Krstic; Li-C. Wang; Kwang-Ting Cheng; Jing-Jia Liou; Magdy S. Abadir (DATE, 2003)

On Structural vs. Functional Testing for Delay Faults. - Angela Krstic; Jing-Jia Liou; Kwang-Ting Cheng; Li-C. Wang (ISQED, 2003)

Diagnosis of Delay Defects Using Statistical Timing Models. - Angela Krstic; Li-C. Wang; Kwang-Ting Cheng; Jing-Jia Liou (VTS, 2003)

Critical Path Selection for Deep Sub-Micron Delay Test and Timing Validation. - Jing-Jia Liou; Li-C. Wang; Angela Krstic; Kwang-Ting (Tim) Cheng (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices. - Jing-Jia Liou; Angela Krstic; Yi-Min Jiang; Kwang-Ting Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

An Application-Independent Delay Testing Methodology for Island-Style FPGA. - Yen-Lin Peng; Jing-Jia Liou; Chih-Tsun Huang; Cheng-Wen Wu (DFT, 2004)

Critical path selection for delay fault testing based upon a statistical timing model. - Li-C. Wang; Jing-Jia Liou; Kwang-Ting Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Diagnosis framework for locating failed segments of path delay faults. - Ying-Yen Chen; Min-Pin Kuo; Jing-Jia Liou (ITC, 2005)

A BIST Scheme for FPGA Interconnect Delay Faults. - Chun-Chieh Wang; Jing-Jia Liou; Yen-Lin Peng; Chih-Tsun Huang; Cheng-Wen Wu (VTS, 2005)

Enhancing Diagnosis Resolution For Delay Faults By Path Extension Method. - Ying-Yen Chen; Jing-Jia Liou (DFT, 2006)

Exploring linear structures of critical path delay faults to reduce test efforts. - Shun-Yen Lu; Pei-Ying Hsieh; Jing-Jia Liou (ICCAD, 2006)

Extraction of Statistical Timing Profiles Using Test Data. - Ying-Yen Chen; Jing-Jia Liou (DAC, 2007)

An efficient SAT-based path delay fault ATPG with an unified sensitization model. - Shun-Yen Lu; Ming-Ting Hsieh; Jing-Jia Liou (ITC, 2007)

A prototype of a wireless-based test system. - Jing-Jia Liou; Chih-Tsun Huang; Cheng-Wen Wu; Ching-Cheng Tien; Chi-Hu Wang; Hsi-Pin Ma; Ying-Yen Chen; Yueh-Chih Hsu; Li-Ming Denq; Chien-Jung Chiu; Young-Wey Li; Chieh-Ming Chang (SoCC, 2007)

Handling Pattern-Dependent Delay Faults in Diagnosis. - Jyun-Wei Chen; Ying-Yen Chen; Jing-Jia Liou (VTS, 2007)

BIST-based diagnosis scheme for field programmable gate array interconnect delay faults. - Yen-Lin Peng; Cheng-Wen Wu; Jing-Jia Liou; Chih-Tsun Huang (IET Comput. Digit. Tech., 2007)

High Quality Pattern Generation for Delay Defects with Functional Sensitized Paths. - Ming-Ting Hsieh; Shun-Yen Lu; Jing-Jia Liou; Augusli Kifli (ATS, 2008)

Area and Test Cost Reduction for On-Chip Wireless Test Channels with System-Level Design Techniques. - Chun-Kai Hsu; Li-Ming Denq; Mao-Yin Wang; Jing-Jia Liou; Chih-Tsun Huang; Cheng-Wen Wu (ATS, 2008)

Diagnosis Framework for Locating Failed Segments of Path Delay Faults. - Ying-Yen Chen; Jing-Jia Liou (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Multiple-Core under Test Architecture for HOY Wireless Testing Platform. - Sung-Yu Chen; Ying-Yen Chen; Chun-Yu Yang; Jing-Jia Liou (Asian Test Symposium, 2009)

A Non-Intrusive and Accurate Inspection Method for Segment Delay Variabilities. - Ying-Yen Chen; Jing-Jia Liou (Asian Test Symposium, 2009)

AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects. - Tsung-Yeh Li; Shi-Yu Huang; Hsuan-Jung Hsu; Chao-Wen Tzeng; Chih-Tsun Huang; Jing-Jia Liou; Hsi-Pin Ma; Po-Chiun Huang; Jenn-Chyou Bor; Cheng-Wen Wu; Ching-Cheng Tien; Mike Wang (DFT, 2010)

Automatic Test Wrapper Synthesis for a Wireless ATE Platform. - Chun-Yu Yang; Ying-Yen Chen; Sung-Yu Chen; Jing-Jia Liou (IEEE Des. Test Comput., 2010)

TurboVG: A HW/SW co-designed multi-core OpenVG accelerator for vector graphics applications with embedded power profiler. - Shuo-Hung Chen; Hsiao-Mei Lin; Ching-Chou Hsieh; Chih-Tsun Huang; Jing-Jia Liou; Yeh-Ching Chung (ASP-DAC, 2011)

Diagnosis-assisted supply voltage configuration to increase performance yield of cell-based designs. - Jing-Jia Liou; Ying-Yen Chen; Chun-Chia Chen; Chung-Yen Chien; Kuo-Li Wu (ASP-DAC, 2011)

A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing. - Chin-Fu Li; Chi-Ying Lee; Chen-Hsing Wang; Shu-Lin Chang; Li-Ming Denq; Chun-Chuan Chi; Hsuan-Jung Hsu; Ming-Yi Chu; Jing-Jia Liou; Shi-Yu Huang; Po-Chiun Huang; Hsi-Pin Ma; et al. (DAC, 2011)

Sampling Correlation Sources for Timing Yield Analysis of Sequential Circuits with Clock Networks. - Lee-eun Yu; Changsik Shin; Seungwhun Paik; Jing-Jia Liou; Youngsoo Shin (J. Circuits Syst. Comput., 2011)

Design and analysis of a many-core processor architecture for multimedia applications. - Jyu-Yuan Lai; Po-Yu Chen; Ting-Shuo Hsu; Chih-Tsun Huang; Jing-Jia Liou (APSIPA, 2012)

On error modeling of electrical bugs for post-silicon timing validation. - Ming Gao; Peter Lisherness; Kwang-Ting Cheng; Jing-Jia Liou (ASP-DAC, 2012)

Test Cost Reduction for Performance Yield Recovery by Classification of Multiple-Clock Test Data. - Jun-Hua Kuo; Ting-Shuo Hsu; Jing-Jia Liou (Asian Test Symposium, 2012)

A Region-Based Framework for Design Feature Identification of Systematic Process Variations. - Shuo-You Hsu; Chih-Hsiang Hsu; Ting-Shuo Hsu; Jing-Jia Liou (Asian Test Symposium, 2013)

Design of high-throughput Inter-PE communication with application-level flow control protocol for many-core architectures. - Jyu-Yuan Lai; Ting-Shuo Hsu; Po-Yu Chen; Chih-Tsun Huang; Yu-Hsun Chen; Jing-Jia Liou (MES, 2013)

AC-Plus Scan Methodology for Small Delay Testing and Characterization. - Tsung-Yeh Li; Shi-Yu Huang; Hsuan-Jung Hsu; Chao-Wen Tzeng; Chih-Tsun Huang; Jing-Jia Liou; Hsi-Pin Ma; Po-Chiun Huang; Jenn-Chyou Bor; Ching-Cheng Tien; Chi-Hu Wang; Cheng-Wen Wu (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Chip clustering with mutual information on multiple clock tests and its application to yield tuning. - Jiun-Yi Chiang; Jun-Hua Kuo; Ting-Shuo Hsu; Jing-Jia Liou (ICCD, 2014)

Methodology of exploring ESL/RTL many-core platforms for developing embedded parallel applications. - Jyu-Yuan Lai; Chih-Tsun Huang; Ting-Shuo Hsu; Jing-Jia Liou; Tung-Hua Yeh; Liang-Chia Cheng; Juin-Ming Lu (SoCC, 2014)

Design of a scalable many-core processor for embedded applications. - Hsiao-Wei Chien; Jyun-Long Lai; Chao-Chieh Wu; Chih-Tsun Huang; Ting-Shuo Hsu; Jing-Jia Liou (ASP-DAC, 2015)

A fast and accurate network-on-chip timing simulator with a flit propagation model. - Ting-Shuo Hsu; Jun-Lin Chiu; Chao-Kai Yu; Jing-Jia Liou (ASP-DAC, 2015)

Cost reduction of system-level tests with stressed structural tests and SVM. - Jing-Jia Liou; Meng-Ta Hsieh; Jun-Fei Cherng; Harry H. Chen (VLSI-SoC, 2015)

Pseudo-Multiple-Exposure-Based Tone Fusion With Local Region Adjustment. - Tsun-Hsien Wang; Cheng-Wen Chiu; Wei-Chen Wu; Jen-Wen Wang; Chun-Yi Lin; Ching-Te Chiu; Jing-Jia Liou (IEEE Trans. Multim., 2015)

Post-Silicon Test Flow for Aging Prediction. - Zih-Huan Gao; Hau Hsu; Ting-Shuo Hsu; Jing-Jia Liou (ATS, 2017)

Design space exploration with a cycle-accurate systemC/TLM DRAM controller model. - Ting-Shuo Hsu; Chao-Chieh Wu; Che-Wei Hsu; Chih-Tsun Huang; Jing-Jia Liou; Yao-Hua Chen; Juin-Ming Lu (VLSI-DAT, 2017)

Optimization for application-specific packet-based on-chip interconnects using a cycle-accurate model. - Yu-Ju Shih; Chih-Tsun Huang; Jing-Jia Liou; Jyu-Yuan Lai; Chih-Wea Wang; Chi-Feng Wu (VLSI-DAT, 2017)

A FPGA Implementation of Farneback Optical Flow by High-Level Synthesis. - Chia-Wei Chang; Zi-Qi Zhong; Jing-Jia Liou (FPGA, 2019)

NNSim: A Fast and Accurate SystemC/TLM Simulator for Deep Convolutional Neural Network Accelerators. - Yi-Che Lee; Ting-Shuo Hsu; Chun-Tse Chen; Jing-Jia Liou; Juin-Ming Lu (VLSI-DAT, 2019)

An ISA-level Accurate Fault Simulator for System-level Fault Analysis. - Jiang-Tang Xiao; Ting-Shuo Hsu; Christian M. Fuchs; Yu-Teng Chang; Jing-Jia Liou; Harry H. Chen (ATS, 2020)

Tile-Based Architecture Exploration for Convolutional Accelerators in Deep Neural Networks. - Yang-Tsai Chen; Yu-Xiang Yen; Chun-Tse Chen; Tzu-Yu Chen; Chih-Tsun Huang; Jing-Jia Liou; Juin-Ming Lu (AICAS, 2021)

Analyzing Transient Faults and Functional Error Rates of a RISC-V Core: A Case Study. - Dun-An Yang; Jing-Jia Liou; Harry H. Chen (ATS, 2021)

ACE-Pro: Reduction of Functional Errors with ACE Propagation Graph. - Dun-An Yang; Yu-Teng Chang; Ting-Shuo Hsu; Jing-Jia Liou; Harry H. Chen (ITC, 2021)

Fast DNN-based Mechatronics Prototyping Platform on Robotic Arm Control. - Yu-Chien Chung; Hao-Hsiang Lian; Yong-Lun Xiao; Chih-Tsun Huang; Jing-Jia Liou (AICAS, 2022)

FPGA-Based Emulation for Accelerating Transient Fault Reduction Analysis. - Zih-Ming Huang; Dun-An Yang; Jing-Jia Liou; Harry H. Chen (ATS, 2022)

Foreword: ATS 2022. - Jin-Fu Li 001; Jing-Jia Liou (ATS, 2022)

Transient Fault Pruning for Effective Candidate Reduction in Functional Debugging. - Dun-An Yang; Jing-Jia Liou; Harry H. Chen (ITC, 2022)

Efficient Segment-wise Pruning for DCNN Inference Accelerators. - Che-Chang Yang; Yung-Tai Shih; Chun-Chen Chen; Chih-Tsun Huang; Jing-Jia Liou; Yao-Hua Chen; Juin-Ming Lu (VLSI-DAT, 2022)

Signal Reduction of Signature Blocks for Transient Fault Debugging. - Chun-Yeh Wang; Chien-Hsing Liang; Jing-Jia Liou; Harry H. Chen (ATS, 2023)

MultiFuse: Efficient Cross Layer Fusion for DNN Accelerators with Multi-level Memory Hierarchy. - Chia-Wei Chang; Jing-Jia Liou; Chih-Tsun Huang; Wei-Chung Hsu; Juin-Ming Lu (ICCD, 2023)

HierArch: A Cluster-Based DNN Accelerator with Hierarchical Buses for Design Space Exploration. - Jyun-Siou Huang; Ting-Han Chou; Juin-Ming Lu; Chih-Tsun Huang; Jing-Jia Liou (SOCC, 2023)