Glitch-Free Multi-Modulus Frequency Divider for Quantization Noise suppression in fractional-N PLLs. - Xiaoming Liu 008; Jing Jin 005; Xi Li; Jianjun Zhou (ISCAS, 2011)

Linear range extensible Phase Frequency Detector and Charge Pump for fast frequency acquisition. - Xiaoming Liu 008; Jing Jin 005; Cui Mao; Jianjun Zhou (ISCAS, 2011)

Anti-interference pseudo-differential wideband LNA for DVB-S.2 RF tuners. - Hui Wang 023; Wufeng Wang; Jing Jin 005; Dongpo Chen; Jianjun Zhou (ISCAS, 2012)

Quantization Noise Suppression in Fractional-N PLLs Utilizing Glitch-Free Phase Switching Multi-Modulus Frequency Divider. - Jing Jin 005; Xiaoming Liu 008; Tingting Mo; Jianjun Zhou (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

Injection-Locking Frequency Divider based dual-modulus prescalers with extended locking range. - Jing Jin 005; Bukun Pan; Xiaoming Liu 008; Jianjun Zhou (ISCAS, 2014)

Digital spur calibration of multi-modulus fractional frequency LO divider utilizing most correlated comparison algorithm. - Jing Jin 005; Bukun Pan; Xiaoming Liu 008; Jianjun Zhou (ISCAS, 2014)

A GHz-level ring-counter-based multi-modulus fractional LO divider with on-the-fly tunability. - Bukun Pan; Jing Jin 005; Jianjun Zhou (ASICON, 2015)

Wideband dual-mode complementary metal-oxide-semiconductor receiver. - Rui Guan; Jing Jin 005; Wenjie Pan; Dongpo Chen; Jianjun Zhou (IET Circuits Devices Syst., 2016)

Analysis of Input LCR Matched N-Path Filter. - Zhijian Lu; Jing Jin 005; Tingting Mo; Jianjun Zhou (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

A high-speed low-power charge pump with dynamic current matching. - Licheng Xu; Xinchi Gao; Jing Jin 005 (ASICON, 2017)

A passive mixer-first receiver with negative feedback for impedance matching. - Shaoqin Yao; Litong Liu; Jing Jin 005 (ASICON, 2017)

A wideband simplified transformer-based VCO with digital amplitude calibration. - Xinchi Gao; Licheng Xu; Jing Jin 005; Naifeng Jing; Jianjun Zhou (MWSCAS, 2017)

A Reconfigurable 28/56 Gb/s PAM4/NRZ Dual-mode SerDes with Hardware-reuse. - Heng Liu; Li Ding; Jing Jin 005; Jianjun Zhou (ISCAS, 2018)

A 28 Gb/s 2-Tap FFE Source-Series-Terminated Transmitter in 22 nm CMOS FDSOI. - Hanchun Tang; Li Ding; Jing Jin 005; Jianjun Zhou (ISCAS, 2018)

16-bit 1-MS/s SAR ADC with foreground digital-domain calibration. - Rui Guan; Jianfeng Xue; Chao Yang; Jing Jin 005; Jianjun Zhou (IET Circuits Devices Syst., 2018)

A low-cost digital-domain foreground calibration for high resolution SAR ADCs. - Rui Guan; Jing Jin 005; Jianjun Zhou (Microelectron. J., 2018)

A 16/32Gb/s NRZ/PAM4 Receiver with Dual-Loop CDR and Threshold Voltage Calibration. - Songhao Guo; Li Ding; Jing Jin 005 (ASICON, 2019)

A High-Linear Digital-to-Phase Converter in 40nm CMOS. - Yu Ji; Li Ding; Jing Jin 005 (ASICON, 2019)

A 0.0558-mm2 0.05-0.9GHz Low-Power Multi-phase Non-overlap Clock Generator in 40 nm CMOS. - Zhigang Li; Xiaofei Wang; Jing Jin 005 (ASICON, 2019)

An Optimized Modeling Method for Transformer Design. - Yingying Liang; Xiaoming Liu 008; Jing Jin 005 (ASICON, 2019)

A Rapid Scrubbing Technique for SEU Mitigation on SRAM-Based FPGAs. - Sijie Zheng; Hongjun You; Guanghui He; Qin Wang 009; Tao Si; Jianfei Jiang 001; Jing Jin 005; Naifeng Jing (ISCAS, 2019)

Fully Configurable Capacitor-Less Oversampling DC Offset Cancellation for Direct Conversion Receivers. - Jing Jin 005; Xiaoming Liu 008; Taotao Yan; Jianjun Zhou (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A 0.25-dB-Step, 68-dB-Dynamic Range Analog Baseband With Digitally Assisted DCOC and AGC for Multi-Standard TV Applications. - Jing Jin 005; Xiaoming Liu 008; Jianjun Zhou (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A Novel Resistive Memory-based Process-in-memory Architecture for Efficient Logic and Add Operations. - Taozhong Li; Qin Wang 009; Yongxin Zhu 001; Jianfei Jiang 001; Guanghui He; Jing Jin 005; Zhigang Mao; Naifeng Jing (ACM Trans. Design Autom. Electr. Syst., 2019)

Decoupling the Multi-Rate Dataflow Execution in Coarse-Grained Reconfigurable Array. - Tu Hong; Ning Guan; Chen Yin; Qin Wang 009; Jianfei Jiang 001; Jing Jin 005; Guanghui He; Naifeng Jing (ISCAS, 2020)

A Low Power Temperature-Compensated Common-Mode Voltage Detector for Dynamic Amplifiers. - Ran Wang; Yuekang Guo; Jing Jin 005; Xiaoming Liu 008; Naifeng Jing; Jianjun Zhou (ISCAS, 2020)

An Inverter-Based Continuous Time Sigma Delta ADC With Latency-Free DAC Calibration. - Yuekang Guo; Jing Jin 005; Xiaoming Liu 008; Jianjun Zhou (IEEE Trans. Circuits Syst., 2020)

A Multi-Modulus Fractional Divider With TDC Free Calibration Scheme for Mitigation of TX-VCO Pulling. - Litong Liu; Jing Jin 005; Xiaoming Liu 008; Jianjun Zhou (IEEE Trans. Circuits Syst., 2020)

An ISM Band High-Linear Current-Reuse Up-Conversion Mixer With Built-in-Self-Calibration for LOFT and I/Q Imbalance. - Xiaofei Wang; Jing Jin 005; Xiaoming Liu 008; Jianjun Zhou (IEEE Trans. Circuits Syst., 2020)

An Enhanced SSCP for Frequency Drift Suppressing in SSPLL. - Chenyue Shi; Shengyuan Zhou; Jing Jin 005 (ASICON, 2021)

Analysis of SAR ADC Quantization Error and Nonlinearity in PMCW Automotive Radar. - Tao Zhong; Yuekang Guo; Jing Jin 005 (ASICON, 2021)

A Phase Domain Excess Loop Delay Compensation Technique with Latency Optimized Phase Selector for VCO-Based Continuous-Time ΔΣ ADC. - Yuekang Guo; Jing Jin 005; Xiaoming Liu 008; Jianjun Zhou (ISCAS, 2021)

A Ka-Band Quadrature-Hybrid LNA-PS with Gm- Boosting Technique in 40-nm CMOS. - Zhengqi Xu; Ke Wu; Xiaoming Liu 008; Chengyuan Liu; Jing Jin 005; Jianjun Zhou (ISCAS, 2021)

A Low Power PVT Stabilization Technique for Dynamic Amplifier in Pipelined SAR ADC. - Yuekang Guo; Jing Jin 005; Jianjun Zhou (MWSCAS, 2021)

A Center Frequency Calibration Technique for Ring VCO Exploiting Delay-1 Detection. - Yuekang Guo; Qiang Pan; Xiaoming Liu 008; Jing Jin 005 (MWSCAS, 2021)

A Latency-Optimized Lookup Table for Nonlinearity Calibration in VCO-Based Sigma-Delta ADCs. - Yanlin He; Yuekang Guo; Jing Jin 005; Jianjun Zhou (MWSCAS, 2021)

A Linearization Technique for Ring VCO Exploiting Bulk-Modulation. - Qiang Pan; Yuekang Guo; Jing Jin 005; Jianjun Zhou (MWSCAS, 2021)

A Power-Efficient SAR ADC with Optimized Timing-Redistribution Asynchronous SAR Logic in 40-nm CMOS. - Mengying Hu; Jing Jin 005; Yuekang Guo; Xiaoming Liu 008; Jianjun Zhou (Circuits Syst. Signal Process., 2021)

An 8 GHz real-time temperature-compensated PLL with 20.8 ppm/°C temperature coefficient for SerDes applications. - Li Ding; Ke Wu; Jing Jin 005; Jianjun Zhou (Microelectron. J., 2021)

A fully integrated multiphase switched-capacitor DC-DC converter with PFM control and charge sharing loss reduction. - Haopeng Kang; Jing Jin 005; Xiaoming Liu 008; Xiaofei Wang; Pengli Hong; Jianjun Zhou (Microelectron. J., 2021)

A 2.4 GHz receiver with a current-reused inductor-less noise-canceling balun LNA in 40 nm CMOS. - Xiaoming Liu 008; Jing Jin 005; Xiaofei Wang; Jianjun Zhou (Microelectron. J., 2021)

A 3bit/cycle 1GS/s 8-bit SAR ADC Employing Asynchronous Ping-Pong Quantization Scheme. - Yuekang Guo; Xiaoming Liu 008; Jing Jin 005; Jianjun Zhou (ISCAS, 2022)

A Power-Efficient CMOS Image Sensor with In-Sensor Processing and In-Pixel Gain Calibration. - Ke Wu; Yuekang Guo; Jing Jin 005; Xiaoming Liu 008; Jianjun Zhou (MWSCAS, 2022)

A Harmonic Rejecting N-Path Filter with Harmonic Gain Calibration Technique. - Ran Bu; Jing Jin 005; Zhaolin Yang; Yuekang Guo; Jianjun Zhou (Circuits Syst. Signal Process., 2022)

A 0.023-12 GHz ultra-wideband frequency synthesizer with FOMT of -251.8 dB. - Chao Yang; Xiaoming Liu 008; Jing Jin 005; Jianjun Zhou (Microelectron. J., 2022)

An 18.1 mW 50 MHz-BW 76.4 dB-SNDR CTSDM With PVT-Robust VCO Quantizer and Latency-Free Background-Calibrated DAC. - Yuekang Guo; Jing Jin 005; Xiaoming Liu 008; Jianjun Zhou (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Fast-Settling Phase-Locked Loop Utilizing Cycle-Slipping-Elimination PFDCP. - Chao Yang; Xiaoming Liu 008; Jing Jin 005; Yuekang Guo; Jianjun Zhou (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 16/32Gbps Dual-Mode SerDes Transmitter with Linearity Enhanced SST Driver. - Li Ding; Jing Jin 005; Jianjun Zhou (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022)

A 30GHz Bidirectional PA/LNA with Transformer-Based Switchable RC Matching Network. - Hanqi Gao; Jing Jin 005; Zhaolin Yang; Jianjun Zhou; Xiaoming Liu 008 (ASICON, 2023)

A Wideband Inductorless LNA Employing Dual-Loop Feedback for Low-Power Applications. - Zhaolin Yang; Jing Jin 005; Yuyang Chen; Jianjun Zhou; Xiaoming Liu 008 (ASICON, 2023)

A 24/48 Gb/s NRZ/PAM-4 Dual-Mode Transmitter with 3-tap FFE in 28 nm CMOS. - Jiaxu Zhou; Jing Jin 005; Yichao Lin; Shan Wang; Bo Wang; Tingting Mo (ASICON, 2023)

Fast locking Sampling PLL Using Phase Error Eliminator. - Shengyuan Zhou; Ziyao Xia; Chao Yang; Xiaoming Liu 008; Sheng Wang; Jing Jin 005 (ASICON, 2023)

A LUT-based Background Linearization Technique for VCO-based ADC Employing $K_{ text{VCO}}- text{Locked}- text{Loop}$. - Yuekang Guo; Jing Jin 005; Xiaoming Liu 008; Zhaolin Yang; Jianjun Zhou (ISCAS, 2023)

An ADPLL with Two-Point Modulation Gain Calibration for 2.4GHz ISM-Band in 40nm CMOS. - Huzhi Tang; Xiaoming Liu 008; Chao Yang; Jing Jin 005 (ISCAS, 2023)

A 16/32-Gb/s/pin Dual-Mode Single-Ended Transmitter with Pre-Emphasis FFE and RLM-Enhanced ZQ Calibration for Memory Interfaces. - Xiaofei Wang; Jing Jin 005; Xiaoming Liu 008; Zhaolin Yang; Shan Wang; Jianjun Zhou (ISCAS, 2023)

Predictive LSB-First Successive Approximation for SAR Analog-to-Digital Converters. - Jiayi Chen; Xiaoming Liu 008; Chao Yang; Jing Jin 005; Zhongyuan Chang; Jianjun Zhou (MWSCAS, 2023)

A Fully Synthesizable Dynamic Voltage Comparator with Time-Domain Offset Calibration. - Shunyan Wang; Yuekang Guo; Qiang Pan; Xiaoming Liu 008; Shan Wang; Jing Jin 005 (MWSCAS, 2023)

A Non-Linearity Digital Background Calibration Algorithm with Piece-Wise Linear Functions. - Ke Wu; Yuekang Guo; Xiaoming Liu 008; Jing Jin 005; Howard C. Yang; Jianjun Zhou (MWSCAS, 2023)

A 60-MS/s 5-MHz BW Noise-Shaping SAR ADC With Integrated Input Buffer Achieving 84.2-dB SNDR and 97.3-dB SFDR Using Dynamic Level-Shifting and ISI-Error Correction. - Yuekang Guo; Jing Jin 005; Xiaoming Liu 008; Jianjun Zhou (IEEE J. Solid State Circuits, 2023)

A Compact 0.2-1.6 GHz 20 MHz-Bandwidth Passive-LNA Exploiting an N-Path 1:3 Transformer. - Minjing Lee; Xiaoming Liu 008; Zhaolin Yang; Jing Jin 005; Lin-Sheng Wu (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 372 μW 10 kHz-BW 109.2 dB-SNDR Nested Delta-Sigma Modulator Using Hysteresis-Comparison MSB-Pass Quantization. - Yuekang Guo; Jing Jin 005; Xiaoming Liu 008; Jianjun Zhou (IEEE J. Solid State Circuits, 2023)

A 4 GHz FLL-less fast-locking sampling PLL with gain-boosted sampling phase-frequency detector in 28 nm CMOS. - Chao Yang; Sheng Wang; Xiaoming Liu 008; Jing Jin 005; Jianjun Zhou (Microelectron. J., 2023)

A 16MHz CMOS RC Frequency Reference with ±125ppm Inaccuracy from -40°C to 85°C Enabled by a Capacitively Modulated RC Time Constant (CMT) Generation and a Die-to-Die Error Removal (DDER) Technique. - Runtao Huo; Dingguo Zhang; Jing Jin 005; Jianjun Zhou; Hui Wang 023 (CICC, 2024)

A 470μW 20kHz-BW 107.3dB-SNDR Nested CT DSM Employing Negative-R-Based Cross-RC Filter and Weighted Multi-Threshold MSB-Pass Quantizer. - Jing Jin 005; Yuekang Guo; Meng Xu; Xiaoming Liu 008; Nan Sun; Jianjun Zhou (CICC, 2024)

A Self-Calibrated Sampling Noise Cancellation Technique for Noise-Shaping SAR ADC. - Zhengyuan Lou; Meng Xu; Yuekang Guo; Jing Jin 005; Jianjun Zhou (ISCAS, 2024)

Design and Analysis of a Family of pW-Level Sub-1V CMOS VRGs by Stacking a Current-Source Transistor and a Resistive-Load Transistor. - Tong Zhang; Dingguo Zhang; Jing Jin 005; Patrick P. Mercier; Hui Wang 023 (ISCAS, 2024)

TICA: Timing Slack Inference and Clock Frequency Adaption Technique for a Deeply Pipelined Near-Threshold-Voltage Bitcoin Mining Core. - Jieyu Li; Weifeng He; Bo Zhang 105; Guanghui He; Jing Jin 005; Jun Yang 006; Mingoo Seok (IEEE J. Solid State Circuits, 2024)

A 0.83-pJ/b 20-Gb/s/Pin Single-Ended Transceiver With AC/DC-Coupled Pre-Emphasis FFE and Edge-Dependent Phase-Modulation DFE for Low-Power Memory Controllers. - Xiaofei Wang; Jing Jin 005; Xiaoming Liu 008; Hui Wang 023; Huzhi Tang; Chao Yang; Yuekang Guo; Tingting Mo; Jianjun Zhou (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

An EF-CIFF Noise-Shaping SAR ADC with A Joint Dynamic Amplifier, Comparator and Lossless Passive Summer Structure. - Yuzhi Ai; Yuekang Guo; Zhengyuan Lou; Hui Zhang; Jing Jin 005; Jianjun Zhou (ISCAS, 2025)

A1-GS/s 7-bit 3-then-1 bit/cycle SAR ADC with A Reconfigurable Reference-Embedded Comparator. - Jinwei Wu; Yuekang Guo; Meng Xu; Lingyan Fan; Jing Jin 005; Jianjun Zhou (ISCAS, 2025)

A reconfigurable passive LNA using an N-path switched-capacitor transformer with 2×/3× voltage Gain. - Zhaolin Yang; Xiaoming Liu 008; Jing Jin 005; Jianjun Zhou (Microelectron. J., 2025)

A 14-bit 2.6GS/s RF sampling pipelined ADC in 28nm CMOS. - Hui Zhang; Dawei Dong; Haijun Wang; Dan Li; Yuan Gao; Chaoyi Hu; Hao Xu; Xinlei Song; Jing Jin 005; Yuekang Guo; Lin Cheng (Microelectron. J., 2025)

A two-phase oscillation scheme with direct background correction for VCO-based ADC. - Tao Zhong; Yuekang Guo; Jing Jin 005; Jianjun Zhou (Microelectron. J., 2025)

A 0.2-2.6 GHz Reconfigurable Receiver Using RF-Gain-Adapted Impedance Matching and Gm-Separated IQ-Leakage Suppression Structure in 40-nm CMOS. - Zhaolin Yang; Jing Jin 005; Xiaoming Liu 008; Jianjun Zhou (IEEE Trans. Very Large Scale Integr. Syst., 2025)