Jing Jane Li
Orcid: 0000-0001-5139-938XAffiliations:
- University of Pennsylvania, Philadelphia, PA, USA
- University of Wisconsin-Madison, Electrical and Computer Engineering Department, WI, USA (2015 - 2019)
- IBM T. J. Watson Research Center, New York, NY, USA (former)
- Purdue University, West Lafayette, IN, USA (PhD 2009)
According to our database1,
Jing Jane Li
authored at least 51 papers
between 2007 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2023
ACM Trans. Reconfigurable Technol. Syst., December, 2023
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023
2022
Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022
Augmenting HLS with Zero-Overhead Application-Specific Address Mapping for Optane DCPMM.
Proceedings of the 30th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2022
Proceedings of the ASPLOS '22: 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Lausanne, Switzerland, 28 February 2022, 2022
2021
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021
Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021
When application-specific ISA meets FPGAs: a multi-layer virtualization framework for heterogeneous cloud FPGAs.
Proceedings of the ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021
2020
MEG: A RISCV-based System Emulation Infrastructure for Near-data Processing Using FPGAs and High-bandwidth Memory.
ACM Trans. Reconfigurable Technol. Syst., 2020
Liquid Silicon: A Nonvolatile Fully Programmable Processing-in-Memory Processor With Monolithically Integrated ReRAM.
IEEE J. Solid State Circuits, 2020
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020
2019
CoRR, 2019
CoRR, 2019
Liquid Silicon: A Nonvolatile Fully Programmable Processing-In-Memory Processor with Monolithically Integrated ReRAM for Big Data/Machine Learning Applications.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
Unleashing the Power of Soft Logic for Convolutional Neural Network Acceleration via Product Quantization.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019
MEG: A RISCV-Based System Simulation Infrastructure for Exploring Memory Optimization Using FPGAs and Hybrid Memory Cube.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019
2018
CMA: A Reconfigurable Complex Matching Accelerator for Wire-Speed Network Intrusion Detection.
IEEE Comput. Archit. Lett., 2018
IEEE Comput. Archit. Lett., 2018
Proceedings of the 6th International Conference on Learning Representations, 2018
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018
Liquid Silicon: A Data-Centric Reconfigurable Architecture Enabled by RRAM Technology.
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018
Accelerating Graph Analytics by Co-Optimizing Storage and Access on an FPGA-HMC Platform.
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018
Proceedings of the 2018 IEEE Conference on Computer Vision and Pattern Recognition, 2018
Liquid Silicon-Monona: A Reconfigurable Memory-Oriented Computing Fabric with Scalable Multi-Context Support.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018
2017
IEEE Comput. Archit. Lett., 2017
Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
Boosting the Performance of FPGA-based Graph Processor using Hybrid Memory Cube: A Case for Breadth First Search.
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017
A Mixed-Signal Data-Centric Reconfigurable Architecture enabled by RRAM Technology (Abstract Only).
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017
2016
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
2015
Enabling phase-change memory for data-centric computing: Technology, circuitand system.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2014
1 Mb 0.41 µm<sup>2</sup> 2T-2R Cell Nonvolatile TCAM With Two-Bit Encoding and Clocked Self-Referenced Sensing.
IEEE J. Solid State Circuits, 2014
2012
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
2011
Proceedings of the 37th European Solid-State Circuits Conference, 2011
2010
Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture Perspective.
IEEE Trans. Very Large Scale Integr. Syst., 2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
2009
Variation Estimation and Compensation Technique in Scaled LTPS TFT Circuits for Low-Power Low-Cost Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
An alternate design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs.
ACM J. Emerg. Technol. Comput. Syst., 2008
Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement.
Proceedings of the 45th Design Automation Conference, 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
Proceedings of the 2007 IEEE International Test Conference, 2007
Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
Proceedings of the 44th Design Automation Conference, 2007