Pipelined Dataflow Architecture of a Small Processor. - Juraj Povazanec; Oliver Chiu-sing Choy; Cheong-Fat Chan; Jan Butas; Yeu-qiu Zhang; Jing-Ling Yang; Tin-yan Tang (PDPTA, 1999)

A self-timed divider using a new fast and robust pipeline scheme. - Jing-Ling Yang; Chiu-Sing Choy; Cheong-Fat Chan (IEEE J. Solid State Circuits, 2001)

A Totally Self-Checking Dynamic Asynchronous Datapath. - Jing-Ling Yang; Oliver Chiu-sing Choy; Cheong-Fat Chan; Kong-Pang Pun (Asian Test Symposium, 2002)

Design for Self-Checking and Self-Timed Datapath. - Jing-Ling Yang; Oliver Chiu-sing Choy; Cheong-Fat Chan; Kong-Pang Pun (VTS, 2003)

Pipelines in Dynamic Dual-Rail Circuits. - Jing-Ling Yang; Oliver Chiu-sing Choy; Cheong-Fat Chan; Kong-Pang Pun (PATMOS, 2004)

A high-efficiency strongly self-checking asynchronous datapath. - Jing-Ling Yang; Chiu-sing Choy; Cheong-Fat Chan; Kong-Pang Pun (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

State-Sensitive X-Filling Scheme for Scan Capture Power Reduction. - Jing-Ling Yang; Qiang Xu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Parallel Interleavers Through Optimized Memory Address Remapping. - Jing-Ling Yang (IEEE Trans. Very Large Scale Integr. Syst., 2010)