A Programmable BIST Core for Embedded DRAM. - Chih-Tsun Huang; Jing-Reng Huang; Chi-Feng Wu; Cheng-Wen Wu; Tsin-Yuan Chang (IEEE Des. Test Comput., 1999)

A programmable built-in self-test core for embedded memories. - Chih-Tsun Huang; Jing-Reng Huang; Cheng-Wen Wu (ASP-DAC, 2000)

A realistic fault model for flash memories. - Yea-Ling Horng; Jing-Reng Huang; Tsin-Yuan Chang (Asian Test Symposium, 2000)

An FPGA-based re-configurable functional tester for memory chips. - Jing-Reng Huang; Chee-Kian Ong; Kwang-Ting Cheng; Cheng-Wen Wu (Asian Test Symposium, 2000)

BRAINS: A BIST Compiler for Embedded Memories. - Chuang Cheng; Chih-Tsun Huang; Jing-Reng Huang; Cheng-Wen Wu; Chen-Jong Wey; Ming-Chang Tsai (DFT, 2000)

Automatic Generation of Memory Built-in Self-Test Cores for System-on-Chip. - Kuo-Liang Cheng; Chia-Ming Hsueh; Jing-Reng Huang; Jen-Chieh Yeh; Chih-Tsun Huang; Cheng-Wen Wu (Asian Test Symposium, 2001)

A low-cost CMOS time interval measurement core. - Ming-Jun Hsiao; Jing-Reng Huang; Shao-Shen Yang; Tsin-Yuan Chang (ISCAS (4), 2001)

A built-in timing parametric measurement unit. - Ming-Jun Hsiao; Jing-Reng Huang; Shao-Shen Yang; Tsin-Yuan Chang (ITC, 2001)

A Self-Test Methodology for IP Cores in Bus-Based Programmable SoCs. - Jing-Reng Huang; Madhu K. Iyer; Kwang-Ting Cheng (VTS, 2001)

Embedded-Software-Based Approach to Testing Crosstalk-Induced Faults at On-Chip Buses. - Wei-Cheng Lai; Jing-Reng Huang; Kwang-Ting (Tim) Cheng (VTS, 2001)

Test Scheduling and Test Access Architecture Optimization for System-on-Chip. - Huan-Shan Hsu; Jing-Reng Huang; Kuo-Liang Cheng; Chih-Wea Wang; Chih-Tsun Huang; Cheng-Wen Wu; Youn-Long Lin (Asian Test Symposium, 2002)

Test Scheduling of BISTed Memory Cores for SOC. - Chih-Wea Wang; Jing-Reng Huang; Yen-Fu Lin; Kuo-Liang Cheng; Chih-Tsun Huang; Cheng-Wen Wu; Youn-Long Lin (Asian Test Symposium, 2002)

Gate-Delay Fault Diagnosis Using the Inject-and-Evaluate Paradigm. - Horng-Bin Wang; Shi-Yu Huang; Jing-Reng Huang (DFT, 2002)

An SOC Test Integration Platform and Its Industrial Realization. - Kuo-Liang Cheng; Jing-Reng Huang; Chih-Wea Wang; Chih-Yen Lo; Li-Ming Denq; Chih-Tsun Huang; Shin-Wei Hung; Jye-Yuan Lee (ITC, 2004)

A Built-In Parametric Timing Measurement Unit. - Ming-Jun Hsiao; Jing-Reng Huang; Tsin-Yuan Chang (IEEE Des. Test Comput., 2004)

STEAC: A Platform for Automatic SOC Test Integration. - Chih-Yen Lo; Chen-Hsing Wang; Kuo-Liang Cheng; Jing-Reng Huang; Chih-Wea Wang; Shin-Moe Wang; Cheng-Wen Wu (IEEE Trans. Very Large Scale Integr. Syst., 2007)