Analysis of the Dual-Threshold-Based Shrinking Scheme for Efficient NB-LDPC Decoding. - Jing Tian 004; Jun Lin 001; Zhongfeng Wang 001 (APCCAS, 2018)

An Efficient NB-LDPC Decoding Algorithm for Next-Generation Memories. - Jing Tian 004; Jun Lin 001; Zhongfeng Wang 001 (ISCAS, 2018)

A 21.66 Gbps Nonbinary LDPC Decoder for High-Speed Communications. - Jing Tian 004; Jun Lin 001; Zhongfeng Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Redundancy-Aided Iterative Reliability-Based Majority-Logic Decoding for NB-LDPC Codes. - Suwen Song; Jing Tian 004; Jun Lin 001; Zhongfeng Wang 001 (ASICON, 2019)

A Novel Low-Complexity Joint Coding and Decoding Algorithm for NB-LDPC Codes. - Suwen Song; Jing Tian 004; Jun Lin 001; Zhongfeng Wang 001 (ISCAS, 2019)

Efficient T-EMS Based Decoding Algorithms for High-Order LDPC Codes. - Jing Tian 004; Suwen Song; Jun Lin 001; Zhongfeng Wang 001 (IEEE Access, 2019)

High-Speed Modular Multipliers for Isogeny-Based Post-Quantum Cryptography. - Jing Tian 004; Zhe Liu 001; Jun Lin 001; Zhongfeng Wang 001; Binjing Li (IACR Cryptol. ePrint Arch., 2019)

Modified GII-BCH Codes for Low-Complexity and Low-Latency Encoders. - Wenjie Li 003; Jing Tian 004; Jun Lin 001; Zhongfeng Wang 001 (IEEE Commun. Lett., 2019)

Fast Permutation Architecture on Encrypted Data for Secure Neural Network Inference. - Xiao Hu 007; Jing Tian 004; Zhongfeng Wang 001 (APCCAS, 2020)

An Efficient Accelerator of the Squaring for the Verifiable Delay Function Over a Class Group. - Danyang Zhu; Yifeng Song; Jing Tian 004; Zhongfeng Wang 001; Haobo Yu (APCCAS, 2020)

A Novel Modular Multiplier for Isogeny-Based Post-Quantum Cryptography. - Bo Wu; Jing Tian 004; Xiao Hu 007; Zhongfeng Wang 001 (ISVLSI, 2020)

Ultra-Fast Modular Multiplication Implementation for Isogeny-Based Post-Quantum Cryptography. - Jing Tian 004; Jun Lin 001; Zhongfeng Wang 001 (IACR Cryptol. ePrint Arch., 2020)

Faster Software Implementation of the SIKE Protocol Based on A New Data Representation. - Jing Tian 004; Piaoyang Wang; Zhe Liu 001; Jun Lin 001; Zhongfeng Wang 001; Johann Großschädl (IACR Cryptol. ePrint Arch., 2020)

A Novel Iterative Reliability-Based Majority-Logic Decoder for NB-LDPC Codes. - Suwen Song; Hangxuan Cui; Jing Tian 004; Jun Lin 001; Zhongfeng Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

Optimized Trellis-Based Min-Max Decoder for NB-LDPC Codes. - Jing Tian 004; Suwen Song; Jun Lin 001; Zhongfeng Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

DARM: A Low-Complexity and Fast Modular Multiplier for Lattice-Based Cryptography. - Xiao Hu 007; Minghao Li 001; Jing Tian 004; Zhongfeng Wang 001 (ASAP, 2021)

High-Speed and Scalable FPGA Implementation of the Key Generation for the Leighton-Micali Signature Protocol. - Yifeng Song; Xiao Hu 007; Wenhao Wang; Jing Tian 004; Zhongfeng Wang 001 (ISCAS, 2021)

Low-Latency Architecture for the Parallel Extended GCD Algorithm of Large Numbers. - Danyang Zhu; Jing Tian 004; Zhongfeng Wang 001 (ISCAS, 2021)

A High-Speed Architecture for the Reduction in VDF Based on a Class Group. - Yifeng Song; Danyang Zhu; Jing Tian 004; Zhongfeng Wang 001 (IACR Cryptol. ePrint Arch., 2021)

An Improved Reliability-Based Decoding Algorithm for NB-LDPC Codes. - Suwen Song; Jing Tian 004; Jun Lin 001; Zhongfeng Wang 001 (IEEE Commun. Lett., 2021)

High-Speed FPGA Implementation of SIKE Based on an Ultra-Low-Latency Modular Multiplier. - Jing Tian 004; Bo Wu; Zhongfeng Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Fast Modular Multipliers for Supersingular Isogeny-Based Post-Quantum Cryptography. - Jing Tian 004; Jun Lin 001; Zhongfeng Wang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2021)

High-Speed and Low-Complexity Modular Reduction Design for CRYSTALS-Kyber. - Minghao Li 001; Jing Tian 004; Xiao Hu 007; Yuan Cao 003; Zhongfeng Wang 001 (APCCAS, 2022)

A High-Speed Codec Architecture for Lagrange Coded Computing. - Bohang Xiong; Jing Tian 004; Zhongfeng Wang 001 (ISCAS, 2022)

An RS-BCH Concatenated FEC Code for Beyond 400 Gb/s Networking. - Lei Yang; Jing Tian 004; Bo Wu; Zhongfeng Wang 001; Hao Ren (ISVLSI, 2022)

Reduction-Free Multiplication for Finite Fields and Polynomial Rings. - Samira Carolina Oliva Madrigal; Gökay Saldamli; Chen Li; Yue Geng; Jing Tian 004; Zhongfeng Wang 001; Çetin Kaya Koç (WAIFI, 2022)

Efficient Software Implementation of the SIKE Protocol Using a New Data Representation. - Jing Tian 004; Piaoyang Wang; Zhe Liu 001; Jun Lin 001; Zhongfeng Wang 001; Johann Großschädl (IEEE Trans. Computers, 2022)

Efficient Homomorphic Convolution Designs on FPGA for Secure Inference. - Xiao Hu 007; Minghao Li 001; Jing Tian 004; Zhongfeng Wang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Efficient FPGA-Based Accelerator of the L-BFGS Algorithm for IoT Applications. - Huiyang Xiong; Bohang Xiong; Wenhao Wang; Jing Tian 004; Hao Zhu 004; Zhongfeng Wang 001 (ISCAS, 2023)

High-Throughput Hardware Implementation for Haraka in SPHINCS+. - Yueqin Dai; Yifeng Song; Jing Tian 004; Zhongfeng Wang 001 (ISQED, 2023)

Efficient Decryption Architecture for Classic McEliece. - Xinyuan Qiao; Suwen Song; Jing Tian 004; Zhongfeng Wang 001 (ISQED, 2023)

An Efficient Hardware Design for Fast Implementation of HQC. - Chen Li; Suwen Song; Jing Tian 004; Zhongfeng Wang 001; Çetin Kaya Koç (SOCC, 2023)

Reconfigurable and High-Efficiency Polynomial Multiplication Accelerator for CRYSTALS-Kyber. - Minghao Li 001; Jing Tian 004; Xiao Hu 007; Zhongfeng Wang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Low-Latency Design and Implementation of the Squaring in Class Groups for Verifiable Delay Function Using Redundant Representation. - Danyang Zhu; Rongrong Zhang; Lun Ou; Jing Tian 004; Zhongfeng Wang 001 (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023)

A High-Speed FPGA-Based Hardware Implementation for Leighton-Micali Signature. - Yifeng Song; Xiao Hu 007; Jing Tian 004; Zhongfeng Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

AC-PM: An Area-Efficient and Configurable Polynomial Multiplier for Lattice Based Cryptography. - Xiao Hu 007; Jing Tian 004; Minghao Li 001; Zhongfeng Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Low-latency Hardware Architecture for VDF Evaluation in Class Groups. - Danyang Zhu; Jing Tian 004; Minghao Li 001; Zhongfeng Wang 001 (IEEE Trans. Computers, 2023)

Fast Hardware Implementation for Extended GCD of Large Numbers in Redundant Representation. - Lun Ou; Danyang Zhu; Jing Tian 004; Zhongfeng Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

An Improved Two-Step Attack on CRYSTALS-Kyber. - Kai Wang; Dejun Xu; Jing Tian 004 (CoRR, 2024)

A Fast and Efficient SIKE Co-Design: Coarse-Grained Reconfigurable Accelerators with Custom RISC-V Microcontroller on FPGA. - Jing Tian 004; Bo Wu; Lang Feng 001; Haochen Zhang; Zhongfeng Wang 001 (IACR Cryptol. ePrint Arch., 2024)

High-Performance FPGA-Based Accelerator of L-BFGS for 3D Face Reconstruction. - Haoran Pan; Bohang Xiong; Jing Tian 004; Shikun Zhang; Hao Zhu 004; Zhongfeng Wang 001 (ISVLSI, 2025)

Fast Scloud+: A Fast Hardware Implementation for the Unstructured LWE-based KEM - Scloud+. - Jing Tian 004; Yaodong Wei; Dejun Xu; Kai Wang; Anyu Wang; Zhiyuan Qiu; Fu Yao; Guang Zeng (IACR Cryptol. ePrint Arch., 2025)

HRCIM-NTT: An Efficient Compute-in-Memory NTT Accelerator With Hybrid-Redundant Numbers. - Xu Zhang 040; Yaodong Wei; Minghao Li 001; Jing Tian 004; Zhongfeng Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

Fast Hardware Architecture With Efficient Matrix Computations for the Key Generation of Classic McEliece. - Haochen Zhang; Xinyuan Qiao; Jing Tian 004; Suwen Song; Zhongfeng Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A Hardware-Friendly Shuffling Countermeasure Against Side-Channel Attacks for Kyber. - Dejun Xu; Kai Wang; Jing Tian 004 (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

An Improved Two-Step Attack on Lattice-Based Cryptography: A Case Study of Kyber. - Kai Wang; Dejun Xu; Jing Tian 004 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)