A Hybrid Anti-Collision Algorithm for RFID with Enhanced Throughput and Reduced Memory Consumption. - Majun Zheng; Jing Xie 010; Zhigang Mao; Yongxin Zhu 001 (EUC (1), 2008)

A novel hardware prefetching scheme exploiting 2-D spatial locality in multimedia applications. - Jin Huang; Jing Xie 010; Zhigang Mao (ASICON, 2011)

A reconfigurable linear array processor architecture for data parallel and computation intensive applications. - Yucheng Liu; Jing Xie 010; Zhigang Mao (ASICON, 2011)

On-chip structure and addressing scheme design for 2-D block data processing in a 64-core array system. - Jing Xie 010; Huimin Xing; Zhigang Mao (VLSI-SoC, 2011)

TSVs-aware floorplanning for 3D integrated circuit. - Jieliang Lu; Qin Wang 009; Jing Xie 010; Zhigang Mao (ASICON, 2013)

A novel architecture scheme with adaptive pipeline coupling technique for DSP processor design. - Zheng Tang; Jing Xie 010; Zhigang Mao (ASICON, 2013)

Modeling and analysis of signal transmission with Through Silicon Via (TSV) noise coupling. - Zhenyang Chen; Qin Wang 009; Jing Xie 010; Jin Tian; Jianfei Jiang 001; Yufei Li; Wen Yin (ISCAS, 2013)

Fault detection and redundancy design for TSVs in 3D ICs. - Sai Hu; Qin Wang 009; Zheng Guo 001; Jing Xie 010; Zhigang Mao (ASICON, 2015)

A crosstalk avoidance scheme based on re-layout of signal TSV. - Jiayi Hu; Qin Wang 009; Jianfei Jiang 001; Jing Xie 010; Zhigang Mao (ASICON, 2015)