Fault-tolerant matrix arithmetic and signal processing on highly concurrent computing structures. - Jing-Yang Jou; Jacob A. Abraham (Proc. IEEE, 1986)

BECOME: Behavior Level Circuit Synthesis Based on Structure Mapping. - Ruey-Sing Wei; Steven G. Rothweiler; Jing-Yang Jou (DAC, 1988)

A testable PLA design with low overhead and ease of test generation. - Jing-Yang Jou (ICCD, 1988)

Fault-Tolerant Algorithms and Architectures for Real Time Signal Processing. - Jing-Yang Jou; Jacob A. Abraham (ICPP (1), 1988)

Fault-Tolerant FFT Networks. - Jing-Yang Jou; Jacob A. Abraham (IEEE Trans. Computers, 1988)

OPAM: an efficient output phase assignment for multilevel logic minimization. - Chin-Long Wey; Sin-Min Chang; Jing-Yang Jou (ICCD, 1989)

A Single-State-Transition Fault Model for Sequential Machines. - Kwang-Ting Cheng; Jing-Yang Jou (ICCAD, 1990)

Functional test generation for finite state machines. - Kwang-Ting Cheng; Jing-Yang Jou (ITC, 1990)

A functional fault model for sequential machines. - Kwang-Ting Cheng; Jing-Yang Jou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

An effective BIST design for PLA. - Jing-Yang Jou (Asian Test Symposium, 1995)

Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture. - Juinn-Dar Huang; Jing-Yang Jou; Wen-Zen Shen (ICCAD, 1995)

Timing-Driven Partial Scan. - Jing-Yang Jou; Kwang-Ting (Tim) Cheng (IEEE Des. Test Comput., 1995)

An Efficient PRPG Strategy By Utilizing Essential Faults. - Li-Ren Huang; Jing-Yang Jou; Sy-Yen Kuo (Asian Test Symposium, 1996)

Easily Testable Data Path Allocation Using Input/Output Registers. - Li-Ren Huang; Jing-Yang Jou; Sy-Yen Kuo; Wen-Bin Liao (Asian Test Symposium, 1996)

An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping. - Juinn-Dar Huang; Jing-Yang Jou; Wen-Zen Shen (ICCAD, 1996)

A power modeling and characterization method for the CMOS standard cell library. - Jiing-Yuan Lin; Wen-Zen Shen; Jing-Yang Jou (ICCAD, 1996)

BDD based lambda set selection in Roth-Karp decomposition for LUT architecture. - Jie-Hong R. Jiang; Jing-Yang Jou; Juinn-Dar Huang; Jung-Shian Wei (ASP-DAC, 1997)

A power driven two-level logic optimizer. - Jyh-Mou Tseng; Jing-Yang Jou (ASP-DAC, 1997)

A power modeling and characterization method for macrocells using structure information. - Jiing-Yuan Lin; Wen-Zen Shen; Jing-Yang Jou (ICCAD, 1997)

Power Driven Partial Scan. - Jing-Yang Jou; Ming-Chang Nien (ICCD, 1997)

Gauss-elimination-based generation of multiple seed-polynomial pairs for LFSR. - Li-Ren Huang; Jing-Yang Jou; Sy-Yen Kuo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Verification Pattern Generation for Core-Based Design Using Port Order Fault Model. - Shing-Wu Tung; Jing-Yang Jou (Asian Test Symposium, 1998)

Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis. - Jie-Hong Roland Jiang; Jing-Yang Jou; Juinn-Dar Huang (DAC, 1998)

A Logical Fault Model for Library Coherence Checking. - Shing-Wu Tung; Jing-Yang Jou (J. Inf. Sci. Eng., 1998)

On circuit clustering for area/delay tradeoff under capacity and pin constraints. - Juinn-Dar Huang; Jing-Yang Jou; Wen-Zen Shen; Hsien-Ho Chuang (IEEE Trans. Very Large Scale Integr. Syst., 1998)

Hierarchical Floorplan Design on the Internet. - Jiann-Horng Lin; Jing-Yang Jou; Iris Hui-Ru Jiang (ASP-DAC, 1999)

Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation. - Iris Hui-Ru Jiang; Jing-Yang Jou; Yao-Wen Chang (DAC, 1999)

Computing Minimum Feedback Vertex Sets by Contraction Operations and its Applications on CAD. - Hen-Ming Lin; Jing-Yang Jou (ICCD, 1999)

An Efficient Functional Coverage Test for HDL Descriptions at RTL. - Chien-Nan Jimmy Liu; Jing-Yang Jou (ICCD, 1999)

Two-level logic minimization for low power. - Jyh-Mou Tseng; Jing-Yang Jou (ACM Trans. Design Autom. Electr. Syst., 1999)

A structure-oriented power modeling technique for macrocells. - Jiing-Yuan Lin; Wen-Zen Shen; Jing-Yang Jou (IEEE Trans. Very Large Scale Integr. Syst., 1999)

A new method for constructing IP level power model based on power sensitivity. - Heng-Liang Huang; Jiing-Yuan Lin; Wen-Zen Shen; Jing-Yang Jou (ASP-DAC, 2000)

Collaboration between Industry and Academia in Test Research. - Kwang-Ting Cheng; Vishwani D. Agrawal; Jing-Yang Jou; Li-C. Wang; Chi-Feng Wu; Shianling Wu (Asian Test Symposium, 2000)

A novel approach for functional coverage measurement in HDL. - Chien-Nan Jimmy Liu; Chen-Yi Chang; Jing-Yang Jou; Ming-Chih Lai; Hsing-Ming Juan (ISCAS, 2000)

Optimal reliable crosstalk-driven interconnect optimization. - Iris Hui-Ru Jiang; Song-Ra Pan; Yao-Wen Chang; Jing-Yang Jou (ISPD, 2000)

An Automatic Controller Extractor for HDL Descriptions at the RTL. - Chien-Nan Jimmy Liu; Jing-Yang Jou (IEEE Des. Test Comput., 2000)

Crosstalk-driven interconnect optimization by simultaneous gate andwire sizing. - Iris Hui-Ru Jiang; Yao-Wen Chang; Jing-Yang Jou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

On computing the minimum feedback vertex set of a directed graph bycontraction operations. - Hen-Ming Lin; Jing-Yang Jou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

ALTO: an iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping. - Juinn-Dar Huang; Jing-Yang Jou; Wen-Zen Shen (IEEE Trans. Very Large Scale Integr. Syst., 2000)

An efficient design-for-verification technique for HDLs. - Chien-Nan Jimmy Liu; I-Ling Chen; Jing-Yang Jou (ASP-DAC, 2001)

An Improved AVPG Algorithm for SoC Design Verification Using Port Order Fault Model. - Chun-Yao Wang; Shing-Wu Tung; Jing-Yang Jou (Asian Test Symposium, 2001)

On generation of the minimum pattern set for data path elements in SoC design verification based on port order fault model. - Chun-Yao Wang; Shing-Wu Tung; Jing-Yang Jou (HLDVT, 2001)

On placement and routing of wafer scale memory. - Li-An Sung; Iris Hui-Ru Jiang; Yoh-Wen Chang; Jing-Yang Jou; Jiin-Chuan Wu; Tai-Sheng Feng (ICECS, 2001)

Grouped input power sensitive transition an input sequence compaction technique for power estimation. - Heng-Liang Huang; Yeong-Ren Chen; Jing-Yang Jou; Wen-Zen Shen (ISCAS (5), 2001)

On tri-state buffer inference in HDL synthesis. - Hen-Ming Lin; Jing-Yang Jou (ISCAS (5), 2001)

An AVPG for SOC design verification with port order fault model. - Chun-Yao Wang; Shing-Wu Tung; Jing-Yang Jou (ISCAS (5), 2001)

Automatic Functional Vector Generation Using the Interacting FSM Model. - Chien-Nan Jimmy Liu; Chia-Chih Yen; Jing-Yang Jou (ISQED, 2001)

Converter-free multiple-voltage scaling techniques for low-powerCMOS digital design. - Yi-Jong Yeh; Sy-Yen Kuo; Jing-Yang Jou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Unified functional decomposition via encoding for FPGA technology mapping. - Jie-Hong Roland Jiang; Jing-Yang Jou; Juinn-Dar Huang (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Effective Error Diagnosis for RTL Designs in HDLs. - Tai-Ying Jiang; Chien-Nan Jimmy Liu; Jing-Yang Jou (Asian Test Symposium, 2002)

A Practical Approach to Cycle Bound Estimation for Property Checking. - Chia-Chih Yen; Kuang-Chien Chen; Jing-Yang Jou (IWLS, 2002)

Bootstrap Monte Carlo with Adaptive Stratification for Power Estimation. - Heng-Liang Huang; Jing-Yang Jou (J. Circuits Syst. Comput., 2002)

On automatic-verification pattern generation for SoC withport-order fault model. - Chun-Yao Wang; Shing-Wu Tung; Jing-Yang Jou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

An automorphic approach to verification pattern generation for SoC design verification using port-order fault model. - Chun-Yao Wang; Shing-Wu Tung; Jing-Yang Jou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

An efficient IP-level power model for complex digital circuits. - Chih-Yang Hsu; Chien-Nan Jimmy Liu; Jing-Yang Jou (ASP-DAC, 2003)

Simultaneous floorplanning and buffer block planning. - Iris Hui-Ru Jiang; Yao-Wen Chang; Jing-Yang Jou; Kai-Yuan Chao (ASP-DAC, 2003)

An automatic interconnection rectification technique for SoC design integration. - Chun-Yao Wang; Shing-Wu Tung; Jing-Yang Jou (ASP-DAC, 2003)

An efficient approach for error diagnosis in HDL design. - Che-Hua Shih; Jing-Yang Jou (ISCAS (4), 2003)

SoC design integration by using automatic interconnection rectification. - Chun-Yao Wang; Shing-Wu Tung; Jing-Yang Jou (ISCAS (4), 2003)

A Design-for-Verification Technique for Functional Pattern Reduction. - Chien-Nan Jimmy Liu; I-Ling Chen; Jing-Yang Jou (IEEE Des. Test Comput., 2003)

An Efficient Power Model for IP-Level Complex Designs. - Chih-Yang Hsu; Chien-Nan Jimmy Liu; Jing-Yang Jou (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Automatic interconnection rectification for SoC design verification based on the port order fault model. - Chun-Yao Wang; Shing-Wu Tung; Jing-Yang Jou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Optimal design of high fan-in multiplexers via mixed-integer nonlinear programming. - Hsu-Wei Huang; Cheng-Yeh Wang; Jing-Yang Jou (ASP-DAC, 2004)

On compliance test of on-chip bus for SOC. - Hue-Min Lin; Chia-Chih Yen; Che-Hua Shih; Jing-Yang Jou (ASP-DAC, 2004)

Layout techniques for on-chip interconnect inductance reduction. - Shang-Wei Tu; Jing-Yang Jou; Yao-Wen Chang (ASP-DAC, 2004)

Enhancing sequential depth computation with a branch-and-bound algorithm. - Chia-Chih Yen; Jing-Yang Jou (HLDVT, 2004)

Graph Automorphism-Based Algorithm for Determining Symmetric Inputs. - Chen-Ling Chou; Chun-Yao Wang; Geeng-Wei Lee; Jing-Yang Jou (ICCD, 2004)

An efficient logic extraction algorithm using partitioning and circuit encoding. - Lily Huang; Tai-Ying Jiang; Jing-Yang Jou; Heng-Liang Huang (ISCAS (5), 2004)

An efficient approach for hierarchical submodule extraction. - Yi-Wei Lin; Jing-Yang Jou (ISCAS (5), 2004)

RLC effects on worst-case switching pattern for on-chip buses. - Shang-Wei Tu; Jing-Yang Jou; Yao-Wen Chang (ISCAS (2), 2004)

Verification on Port Connections. - Geeng-Wei Lee; Juinn-Dar Huang; Jing-Yang Jou; Chun-Yao Wang (ITC, 2004)

A Divide-and-Conquer-Based Algorithm for Automatic Simulation Vector Generation. - Chia-Chih Yen; Jing-Yang Jou; Kuang-Chien Chen (IEEE Des. Test Comput., 2004)

Simultaneous floor plan and buffer-block optimization. - Iris Hui-Ru Jiang; Yao-Wen Chang; Jing-Yang Jou; Kai-Yuan Chao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

An observability measure to enhance statement coverage metric for proper evaluation of verification completeness. - Tai-Ying Jiang; Chien-Nan Jimmy Liu; Jing-Yang Jou (ASP-DAC, 2005)

Communication-driven task binding for multiprocessor with latency insensitive network-on-chip. - Liang-Yu Lin; Cheng-Yeh Wang; Pao-Jui Huang; Chih-Chieh Chou; Jing-Yang Jou (ASP-DAC, 2005)

Stimulus generation for interface protocol verification using the nondeterministic extended finite state machine model. - Che-Hua Shih; Juinn-Dar Huang; Jing-Yang Jou (HLDVT, 2005)

An optimum algorithm for compacting error traces for efficient functional debugging. - Chia-Chih Yen; Jing-Yang Jou (HLDVT, 2005)

Estimating likelihood of correctness for error candidates to assist debugging faulty HDL designs. - Tai-Ying Jiang; Chien-Nan Jimmy Liu; Jing-Yang Jou (ISCAS (6), 2005)

RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction. - Shang-Wei Tu; Jing-Yang Jou; Yao-Wen Chang (ISCAS (4), 2005)

An efficient heterogeneous tree multiplexer synthesis technique. - Hsu-Wei Huang; Cheng-Yeh Wang; Jing-Yang Jou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication. - Chien-Hua Chen; Geeng-Wei Lee; Juinn-Dar Huang; Jing-Yang Jou (ASP-DAC, 2006)

FSM-based transaction-level functional coverage for interface compliance verification. - Man-Yun Su; Che-Hua Shih; Juinn-Dar Huang; Jing-Yang Jou (ASP-DAC, 2006)

Multi-Project System-on-Chip (MP-SoC): A Novel Test Vehicle for SoC Silicon Prototyping. - Chun-Ming Huang; Kuen-Jong Lee; Chih-Chyau Yang; Wen-Hsiang Hu; Shi-Shen Wang; Jeng-Bin Chen; Chi-Shi Chen; Lan-Da Van; Chien-Ming Wu; Wei-Chang Tsai; Jing-Yang Jou (SoCC, 2006)

An Optimum Algorithm for Compacting Error Traces for Efficient Design Error Debugging. - Chia-Chih Yen; Jing-Yang Jou (IEEE Trans. Computers, 2006)

RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction. - Shang-Wei Tu; Yao-Wen Chang; Jing-Yang Jou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Reliable crosstalk-driven interconnect optimization. - Iris Hui-Ru Jiang; Song-Ra Pan; Yao-Wen Chang; Jing-Yang Jou (ACM Trans. Design Autom. Electr. Syst., 2006)

A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC Buses. - Bu-Ching Lin; Geeng-Wei Lee; Juinn-Dar Huang; Jing-Yang Jou (ASP-DAC, 2007)

A Tableless Approach for High-Level Power Modeling Using Neural Networks. - Chih-Yang Hsu; Wen-Tsan Hsieh; Chien-Nan Jimmy Liu; Jing-Yang Jou (J. Inf. Sci. Eng., 2007)

Hybrid Wordlength Optimization Methods of Pipelined FFT Processors. - Cheng-Yeh Wang; Chih-Bin Kuo; Jing-Yang Jou (IEEE Trans. Computers, 2007)

Observability Analysis on HDL Descriptions for Effective Functional Validation. - Tai-Ying Jiang; Chien-Nan Jimmy Liu; Jing-Yang Jou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Crosstalk-avoidance coding for low-power on-chip bus. - Kuang-Chin Cheng; Jing-Yang Jou (ICECS, 2008)

Verification of Pin-Accurate Port Connections. - Geeng-Wei Lee; Juinn-Dar Huang; Chun-Yao Wang; Jing-Yang Jou (IEEE Des. Test Comput., 2008)

Multiple-Fault Diagnosis Using Faulty-Region Identification. - Meng-Jai Tasi; Mango Chia-Tso Chao; Jing-Yang Jou; Meng-Chen Wu (VTS, 2009)

Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging. - Tai-Ying Jiang; Chien-Nan Jimmy Liu; Jing-Yang Jou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Performance-constrained voltage assignment in multiple supply voltage SoC floorplanning. - Meng-Chen Wu; Ming-Ching Lu; Hung-Ming Chen; Jing-Yang Jou (ACM Trans. Design Autom. Electr. Syst., 2009)

Automatic Verification Stimulus Generation for Interface Protocols Modeled With Non-Deterministic Extended FSM. - Che-Hua Shih; Juinn-Dar Huang; Jing-Yang Jou (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Unleash the parallelism of 3DIC partitioning on GPGPU. - Hsien-Kai Kuo; Bo-Cheng Charles Lai; Jing-Yang Jou (SoCC, 2010)

Expandable MDC-based FFT architecture and its generator for high-performance applications. - Bu-Ching Lin; Yu-Hsiang Wang; Juinn-Dar Huang; Jing-Yang Jou (SoCC, 2010)

FSM-Based Formal Compliance Verification of Interface Protocols. - Che-Hua Shih; Ya-Ching Yang; Chia-Chih Yen; Juinn-Dar Huang; Jing-Yang Jou (J. Inf. Sci. Eng., 2010)

Equivalence checking of scheduling with speculative code transformations in high-level synthesis. - Chi-Hui Lee; Che-Hua Shih; Juinn-Dar Huang; Jing-Yang Jou (ASP-DAC, 2011)

Mixed non-rectangular block packing for non-Manhattan layout architectures. - Meng-Chen Wu; Hung-Ming Chen; Jing-Yang Jou (ISQED, 2011)

Design-for-debug layout adjustment for FIB probing and circuit editing. - Kuo-An Chen; Tsung-Wei Chang; Meng-Chen Wu; Mango Chia-Tso Chao; Jing-Yang Jou; Sonair Chen (ITC, 2011)

Thread affinity mapping for irregular data access on shared Cache GPGPU. - Hsien-Kai Kuo; Kuan-Ting Chen; Bo-Cheng Charles Lai; Jing-Yang Jou (ASP-DAC, 2012)

A formal method to improve SystemVerilog functional coverage. - An-Che Cheng; Chia-Chih Yen; Jing-Yang Jou (HLDVT, 2012)

Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay. - Juinn-Dar Huang; Chia-I Chen; Wan-Ling Hsu; Yen-Ting Lin; Jing-Yang Jou (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

Cache Capacity Aware Thread Scheduling for Irregular Memory Access on many-core GPGPUs. - Hsien-Kai Kuo; Ta-Kan Yen; Bo-Cheng Charles Lai; Jing-Yang Jou (ASP-DAC, 2013)

A read-write aware DRAM scheduling for power reduction in multi-core systems. - Chih-Yen Lai; Gung-Yu Pan; Hsien-Kai Kuo; Jing-Yang Jou (ASP-DAC, 2014)

A learning-on-cloud power management policy for smart devices. - Gung-Yu Pan; Bo-Cheng Charles Lai; Sheng-Yen Chen; Jing-Yang Jou (ICCAD, 2014)

ILP-Based Bitwidth-Aware Subexpression Sharing for Area Minimization in Multiple Constant Multiplication. - Bu-Ching Lin; Juinn-Dar Huang; Jing-Yang Jou (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Probability-Based Static Scaling Optimization for Fixed Wordlength FFT Processors. - Bu-Ching Lin; Ming-En Shih; Juinn-Dar Huang; Jing-Yang Jou (J. Inf. Sci. Eng., 2014)

Efficient Coverage-Driven Stimulus Generation Using Simultaneous SAT Solving, with Application to SystemVerilog. - An-Che Cheng; Chia-Chih Jack Yen; Celina G. Val; Sam Bayless; Alan J. Hu; Iris Hui-Ru Jiang; Jing-Yang Jou (ACM Trans. Design Autom. Electr. Syst., 2014)

Reducing Contention in Shared Last-Level Cache for Throughput Processors. - Hsien-Kai Kuo; Bo-Cheng Charles Lai; Jing-Yang Jou (ACM Trans. Design Autom. Electr. Syst., 2014)

Scalable Power Management Using Multilevel Reinforcement Learning for Multiprocessors. - Gung-Yu Pan; Jing-Yang Jou; Bo-Cheng Lai (ACM Trans. Design Autom. Electr. Syst., 2014)

Power-Efficient Instancy Aware DRAM Scheduling. - Gung-Yu Pan; Chih-Yen Lai; Jing-Yang Jou; Bo-Cheng Charles Lai (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

A Cache Hierarchy Aware Thread Mapping Methodology for GPGPUs. - Bo-Cheng Charles Lai; Hsien-Kai Kuo; Jing-Yang Jou (IEEE Trans. Computers, 2015)

Scalable Global Power Management Policy Based on Combinatorial Optimization for Multiprocessors. - Gung-Yu Pan; Jed Yang; Jing-Yang Jou; Bo-Cheng Charles Lai (ACM Trans. Embed. Comput. Syst., 2015)

Chain-based pin count minimization for general-purpose digital microfluidic biochips. - Yung-Chun Lei; Chen-Shing Hsu; Juinn-Dar Huang; Jing-Yang Jou (ASP-DAC, 2016)

Resource-aware functional ECO patch generation. - An-Che Cheng; Iris Hui-Ru Jiang; Jing-Yang Jou (DATE, 2016)

Wave digital filter based analog circuit emulation on FPGA. - Wei Wu; Yen-Lung Chen; Yue Ma; Chien-Nan Jimmy Liu; Jing-Yang Jou; Sudhakar Pamarti; Lei He 001 (ISCAS, 2016)

1st-Order to 2nd-Order Threshold Logic Gate Transformation with an Enhanced ILP-based Identification Method. - Li-Cheng Zheng; Hao-Ju Chang; Yung-Chih Chen; Jing-Yang Jou (ASP-DAC, 2021)

Performance-driven Routing Methodology with Incremental Placement Refinement for Analog Layout Design. - Hao-Yu Chi; Han-Chung Chang; Chih-Hsin Yang; Chien-Nan Liu; Jing-Yang Jou (DATE, 2021)

A Reconfigurable Accelerator Design for Quantized Depthwise Separable Convolutions. - Yu-Guang Chen; Hung-Yi Chiang; Chi-Wei Hsu; Tsung-Han Hsieh; Jing-Yang Jou (ISOCC, 2021)

A Hierarchical and Reconfigurable Process Element Design for Quantized Neural Networks. - Yu-Guang Chen; Chi-Wei Hsu; Hung-Yi Chiang; Tsung-Han Hsieh; Jing-Yang Jou (SoCC, 2021)

A Novel DNN Accelerator for Light-weight Neural Networks: Concept and Design. - Yu-Guang Chen; Tsung-Han Hsieh; Yi-Chen Ho; Jing-Yang Jou (AICAS, 2022)

An Evaluation and Architecture Exploration Engine for CNN Accelerators through Extensive Dataflow Analysis. - Shan-Hui Chou; Ting-Yun Hsiao; Jing-Yang Jou; Juinn-Dar Huang (VLSI-SoC, 2023)

TNSS: Two-Nibble Sparsity-Aware Stride-Decomposing Acceleration for Convolutional Neural Networks. - Yun-Yin Huang; Yu-Guang Chen; Jing-Yang Jou (APCCAS, 2024)

Aging Mitigation in Systolic Array Accelerators: Balancing PE Loads for Enhanced Reliability. - Yu-Guang Chen; Yi-Chen Ho; Jing-Yang Jou (SOCC, 2024)