Observation Point Oriented Deterministic Diagnosis Pattern Generation (DDPG) for Chain Diagnosis. - Fei Wang; Yu Hu 001; Yu Huang 005; Jing Ye 001; Xiaowei Li 001 (ATS, 2008)

Deterministic Diagnostic Pattern Generation (DDPG) for Compound Defects. - Fei Wang; Yu Hu 001; Huawei Li 001; Xiaowei Li 001; Jing Ye 001; Yu Huang 005 (ITC, 2008)

Diagnosis of Mask-Effect Multiple Timing Faults in Scan Chains. - Jing Ye 001; Fei Wang; Yu Hu 001; Xiaowei Li 001 (ITC, 2008)

Substantial Fault Pair At-a-Time (SFPAT): An Automatic Diagnostic Pattern Generation Method. - Jing Ye 001; Xiaolin Zhang; Yu Hu 001; Xiaowei Li 001 (Asian Test Symposium, 2010)

Diagnosis of multiple arbitrary faults with mask and reinforcement effect. - Jing Ye 001; Yu Hu 001; Xiaowei Li 001 (DATE, 2010)

On diagnosis of multiple faults using compacted responses. - Jing Ye 001; Yu Hu 001; Xiaowei Li 001 (DATE, 2011)

Capturing post-silicon variation by layout-aware path-delay testing. - Xiaolin Zhang; Jing Ye 001; Yu Hu 001; Xiaowei Li 001 (DATE, 2013)

Diagnose Failures Caused by Multiple Locations at a Time. - Jing Ye 001; Yu Hu 001; Xiaowei Li 001; Wu-Tung Cheng; Yu Huang 005; Huaxing Tang (IEEE Trans. Very Large Scale Integr. Syst., 2014)

OPUF: Obfuscation logic based physical unclonable function. - Jing Ye 001; Yu Hu 001; Xiaowei Li 001 (IOLTS, 2015)

Diagnosis and Layout Aware (DLA) Scan Chain Stitching. - Jing Ye 001; Yu Huang 005; Yu Hu 001; Wu-Tung Cheng; Ruifeng Guo; Liyang Lai; Ting-Pu Tai; Xiaowei Li 001; Wei-pin Changchien; Daw-Ming Lee; Ji-Jan Chen; Sandeep C. Eruvathi; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Efficient Attack on Non-linear Current Mirror PUF with Genetic Algorithm. - Qingli Guo; Jing Ye 001; Yue Gong; Yu Hu 001; Xiaowei Li 001 (ATS, 2016)

POSTER: Attack on Non-Linear Physical Unclonable Function. - Jing Ye 001; Yu Hu 001; Xiaowei Li 001 (CCS, 2016)

DCPUF: Placement and Routing Constraint based Dynamically Configured Physical Unclonable Function on FPGA (Abstact Only). - Jing Ye 001; Yu Hu 001; Xiaowei Li 001 (FPGA, 2016)

TeSHoP: A Temperature Sensing based Hotspot-Driven Placement technique for FPGAs. - Weina Lu; Yu Hu 001; Jing Ye 001; Xiaowei Li 001 (FPL, 2016)

RPUF: Physical Unclonable Function with Randomized Challenge to resist modeling attack. - Jing Ye 001; Yu Hu 001; Xiaowei Li 001 (AsianHOST, 2016)

Fault diagnosis of arbiter physical unclonable function. - Jing Ye 001; Qingli Quo; Yu Hu 001; Xiaowei Li 001 (DATE, 2017)

Leveraging FVT-margins in design space exploration for FFGA-based CNN accelerators. - Weina Lu; Wenyan Lu; Jing Ye 001; Yu Hu 001; Xiaowei Li 001 (FPL, 2017)

Polymorphic PUF: Exploiting reconfigurability of CPU+FPGA SoC to resist modeling attack. - Jing Ye 001; Yue Gong; Yu Hu 001; Xiaowei Li 001 (IOLTS, 2017)

VPUF: Voter based physical unclonable function with high reliability and modeling attack resistance. - Jing Ye 001; Yu Hu 001; Xiaowei Li 001 (IOLTS, 2017)

GeoCueDepth: Exploiting geometric structure cues to estimate depth from a single image. - Yiming Zeng 003; Yu Hu 001; Shice Liu; Qiankun Tang; Jing Ye 001; Xiaowei Li 001 (IROS, 2017)

LAPS: Layout-Aware Path Selection for Post-Silicon Timing Characterization. - Yu Hu 001; Jing Ye 001; Zhiping Shi 002; Xiaowei Li 001 (IEICE Trans. Inf. Syst., 2017)

Power-Utility-Driven Write Management for MLC PCM. - Bing Li 017; Yu Hu 001; Ying Wang 001; Jing Ye 001; Xiaowei Li 001 (ACM J. Emerg. Technol. Comput. Syst., 2017)

Going Cooler With Timing-Constrained TeSHoP: A Temperature Sensing-Based Hotspot-Driven Placement Technique for FPGAs. - Weina Lu; Yu Hu 001; Jing Ye 001; Xiaowei Li 001 (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Bias PUF based Secure Scan Chain Design. - Wenjie Li 004; Jing Ye 001; Xiaowei Li 001; Huawei Li 001; Yu Hu 001 (AsianHOST, 2018)

PUF Based Pay-Per-Device Scheme for IP Protection of CNN Model. - Qingli Guo; Jing Ye 001; Yue Gong; Yu Hu 001; Xiaowei Li 001 (ATS, 2018)

Hardware Trojan in FPGA CNN Accelerator. - Jing Ye 001; Yu Hu 001; Xiaowei Li 001 (ATS, 2018)

VarNet: Exploring Variations for Unsupervised Video Prediction. - Beibei Jin; Yu Hu 001; Yiming Zeng 003; Qiankun Tang; Shice Liu; Jing Ye 001 (IROS, 2018)

Grey Zone in Pre-Silicon Hardware Trojan Detection. - Jing Ye 001; Yipei Yang; Yue Gong; Yu Hu 001; Xiaowei Li 001 (ITC-Asia, 2018)

Modeling attacks on strong physical unclonable functions strengthened by random number and weak PUF. - Jing Ye 001; Qingli Guo; Yu Hu 001; Huawei Li 001; Xiaowei Li 001 (VTS, 2018)

Fault tolerance on-chip: a reliable computing paradigm using self-test, self-diagnosis, and self-repair (3S) approach. - Xiaowei Li 001; Guihai Yan; Jing Ye 001; Ying Wang 001 (Sci. China Inf. Sci., 2018)

RT3D: Real-Time 3-D Vehicle Detection in LiDAR Point Cloud for Autonomous Driving. - Yiming Zeng 003; Yu Hu 001; Shice Liu; Jing Ye 001; Yinhe Han 001; Xiaowei Li 001; Ninghui Sun (IEEE Robotics Autom. Lett., 2018)

Deterministic and Probabilistic Diagnostic Challenge Generation for Arbiter Physical Unclonable Function. - Jing Ye 001; Qingli Guo; Yu Hu 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Memory Trojan Attack on Neural Network Accelerators. - Yang Zhao 013; Xing Hu 001; Shuangchen Li; Jing Ye 001; Lei Deng 003; Yu Ji 002; Jianyu Xu; Dong Wu; Yuan Xie 001 (DATE, 2019)

iATPG: Instruction-level Automatic Test Program Generation for Vulnerabilities under DVFS attack. - Kuozhong Zhang; Junying Huang; Jing Ye 001; Xiaochun Ye; Da Wang; Dongrui Fan; Huawei Li 001; Xiaowei Li 001; Zhimin Zhang 004 (IOLTS, 2019)

Instruction Vulnerability Test and Code Optimization Against DVFS Attack. - Junying Huang; Jing Ye 001; Xiaochun Ye; Da Wang; Dongrui Fan; Huawei Li 001; Xiaowei Li 001; Zhimin Zhang 004 (ITC-Asia, 2019)

Implementation of Parametric Hardware Trojan in FPGA. - Yipei Yang; Jing Ye 001; Xiaowei Li 001; Yinhe Han 001; Huawei Li 001; Yu Hu 001 (ITC-Asia, 2019)

Scan Chain Based Attacks and Countermeasures: A Survey. - Xiaowei Li 001; Wenjie Li 004; Jing Ye 001; Huawei Li 001; Yu Hu 001 (IEEE Access, 2019)

PUFPass: A password management mechanism based on software/hardware codesign. - Qingli Guo; Jing Ye 001; Bing Li 017; Yu Hu 001; Xiaowei Li 001; Yazhu Lan; Guohe Zhang (Integr., 2019)

Survey: Hardware Trojan Detection for Netlist. - Yipei Yang; Jing Ye 001; Yuan Cao 003; Jiliang Zhang 002; Xiaowei Li 001; Huawei Li 001; Yu Hu 001 (ATS, 2020)

HRAE: Hardware-assisted Randomization against Adversarial Example Attacks. - Jiliang Zhang 002; Shuang Peng 010; Yupeng Hu; Fei Peng; Wei Hu 008; Jinmei Lai 001; Jing Ye 001; Xiangqi Wang (ATS, 2020)

Optimization Space Exploration of Hardware Design for CRYSTALS-KYBER. - Yixuan Zhao; Zhiteng Chao; Jing Ye 001; Wen Wang 007; Yuan Cao 003; Shuai Chen; Xiaowei Li 001; Huawei Li 001 (ATS, 2020)

Privacy Threats and Protection in Machine Learning. - Jiliang Zhang 002; Chen Li; Jing Ye 001; Gang Qu 001 (ACM Great Lakes Symposium on VLSI, 2020)

Prediction Stability: A New Metric for Quantitatively Evaluating DNN Outputs. - Qingli Guo; Jing Ye 001; Jiliang Zhang 002; Yu Hu 001; Xiaowei Li 001; Huawei Li 001 (ACM Great Lakes Symposium on VLSI, 2020)

Sequence Triggered Hardware Trojan in Neural Network Accelerator. - Zizhen Liu; Jing Ye 001; Xing Hu 001; Huawei Li 001; Xiaowei Li 001; Yu Hu 001 (VTS, 2020)

MultiPAD: A Multivariant Partition-Based Method for Audio Adversarial Examples Detection. - Qingli Guo; Jing Ye 001; Yu Hu 001; Guohe Zhang; Xiaowei Li 001; Huawei Li 001 (IEEE Access, 2020)

INOR - An Intelligent noise reduction method to defend against adversarial audio examples. - Qingli Guo; Jing Ye 001; Yiran Chen 001; Yu Hu 001; Yazhu Lan; Guohe Zhang; Xiaowei Li 001 (Neurocomputing, 2020)

ChaoPIM: A PIM-based Protection Framework for DNN Accelerators Using Chaotic Encryption. - Ning Lin; Xiaoming Chen 003; Chunwei Xia; Jing Ye 001; Xiaowei Li 001 (ATS, 2021)

Reliability Evaluation of Approximate Arithmetic Circuits Based on Signal Probability. - Zhen Wang 042; Guofa Zhang; Jing Ye 001; Jianhui Jiang (ITC-Asia, 2021)

Efficient Secure Aggregation Based on SHPRG For Federated Learning. - Zizhen Liu; Si Chen; Jing Ye 001; Junfeng Fan; Huawei Li 001; Xiaowei Li 001 (CoRR, 2021)

Practical Attacks on Deep Neural Networks by Memory Trojaning. - Xing Hu 001; Yang Zhao 013; Lei Deng 003; Ling Liang; Pengfei Zuo; Jing Ye 001; Yingyan Lin; Yuan Xie 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

A Voltage Template Attack on the Modular Polynomial Subtraction in Kyber. - Jianan Mu; Yixuan Zhao; Zongyue Wang; Jing Ye 001; Junfeng Fan; Shuai Chen; Huawei Li 001; Xiaowei Li 001; Yuan Cao 003 (ASP-DAC, 2022)

Exploring the high-throughput and low-delay hardware design of SM4 on FPGA. - Yixiao Chen; Jinfeng Song; Shuai Chen; Yuan Cao 003; Jing Ye 001; Huawei Li 001; Xiaowei Li 001; Xin Lou; Enyi Yao (ISOCC, 2022)

SASH: Efficient secure aggregation based on SHPRG for federated learning. - Zizhen Liu; Si Chen; Jing Ye 001; Junfeng Fan; Huawei Li 001; Xiaowei Li 001 (UAI, 2022)

Entropy Sources Based on Silicon Chips: True Random Number Generator and Physical Unclonable Function. - Yuan Cao 003; Wanyi Liu; Lan Qin; Bingqiang Liu; Shuai Chen; Jing Ye 001; Xianzhao Xia; Chao Wang 096 (Entropy, 2022)

An Efficient Full Hardware Implementation of Extended Merkle Signature Scheme. - Yuan Cao 003; Yanze Wu; Wen Wang 007; Xu Lu; Shuai Chen; Jing Ye 001; Chip-Hong Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Accurate Reliability Boundary Evaluation of Approximate Arithmetic Circuit. - Zhen Wang 042; Guofa Zhang; Peng Liu 045; Jing Ye 001; Jianhui Jiang (IEEE Trans. Very Large Scale Integr. Syst., 2022)

A Distributed ATPG System Combining Test Compaction Based on Pure MaxSAT. - Zhiteng Chao; Senlin Wang; Pengyu Tian; Shuwen Yuan; Huawei Li 001; Jing Ye 001; Xiaowei Li 001 (ATS, 2023)

Message from the Chairs. - Huawei Li 001; Jing Ye 001; Wei Hu 008; Jiliang Zhang 002 (ATS, 2023)

Configurable and High-Level Pipelined Lattice-Based Post Quantum Cryptography Hardware Accelerator Design. - Jianan Mu; Huajie Tan; Shuai Chen; Min Cai; Jing Ye 001; Huawei Li 001; Xiaowei Li 001 (ATS, 2023)

A Template Attack on Reduction Without Reference Device on Kyber. - Yipei Yang; Junying Huang; Zongyue Wang; Jing Ye 001; Zihao Sun; Junfeng Fan; Shuai Chen; Huawei Li 001; Xiaowei Li 001; Yuan Cao 003 (ATS, 2023)

Energy-efficient NTT Design with One-bank SRAM and 2-D PE Array. - Jianan Mu; Huajie Tan; Jiawen Wu; Haotian Lu 002; Chip-Hong Chang; Shuai Chen; Shengwen Liang; Jing Ye 001; Huawei Li 001; Xiaowei Li 001 (DATE, 2023)

Online Reliability Evaluation Design: Select Reliable CRPs for Arbiter PUF and Its Variants. - Chaofang Ma; Jianan Mu; Jing Ye 001; Shuai Chen; Yuan Cao 003; Huawei Li 001; Xiaowei Li 001 (ETS, 2023)

Chosen ciphertext correlation power analysis on Kyber. - Yipei Yang; Zongyue Wang; Jing Ye 001; Junfeng Fan; Shuai Chen; Huawei Li 001; Xiaowei Li 001; Yuan Cao 003 (Integr., 2023)

DHSA: efficient doubly homomorphic secure aggregation for cross-silo federated learning. - Zizhen Liu; Si Chen; Jing Ye 001; Junfeng Fan; Huawei Li 001; Xiaowei Li 001 (J. Supercomput., 2023)

Scalable and Conflict-Free NTT Hardware Accelerator Design: Methodology, Proof, and Implementation. - Jianan Mu; Yi Ren; Wen Wang 007; Yizhong Hu; Shuai Chen; Chip-Hong Chang; Junfeng Fan; Jing Ye 001; Yuan Cao 003; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

A New Reconfigurable True Random Number Generator and Physical Unclonable Function Unified Chip With On-Chip Auto-Calibration. - Yuan Cao 003; Wanyi Liu; Yue Zheng; Shuai Chen; Jing Ye 001; Lei Qian; Chip-Hong Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A Fast Test Compaction Method for Commercial DFT Flow Using Dedicated Pure-MaxSAT Solver. - Zhiteng Chao; Xindi Zhang; Junying Huang; Jing Ye 001; Shaowei Cai 001; Huawei Li 001; Xiaowei Li 001 (ASPDAC, 2024)

Accelerating Sequential Circuit Simulation with Spatial Locality Enhancement and Redundant Event Reduction. - Jiaping Tang; Zizhen Liu; Jianan Mu; Feng Gu; Mingjun Wang; Wenxing Li; Jing Ye 001; Xiaowei Li 001; Huawei Li 001 (ATS, 2024)

Alchemist: A Unified Accelerator Architecture for Cross-Scheme Fully Homomorphic Encryption. - Jianan Mu; Husheng Han; Shangyi Shi; Jing Ye 001; Zizhen Liu; Shengwen Liang; Meng Li 004; Mingzhe Zhang; Song Bian 001; Xing Hu 001; Huawei Li 001; Xiaowei Li 001 (DAC, 2024)

A Fully Pipelined High-Performance Elliptic Curve Cryptography Processor for NIST P-256. - Han Yan; Shuai Chen; Junying Huang; Jing Ye 001; Huawei Li 001; Xiaowei Li 001 (ETS, 2024)

DDP-Fsim: Efficient and Scalable Fault Simulation for Deterministic Patterns with Two-Dimensional Parallelism. - Feng Gu; Mingjun Wang; Jianan Mu; Zizhen Liu; Jiaping Tang; Hui Wang 152; Yonghao Wang; Jing Ye 001; Huawei Li 001; Xiaowei Li 001 (ICCAD, 2024)

A Static Test Compaction Method Based on GCN Assisted Fault Gate Classification. - Zhiteng Chao; Qinluan Dai; Jiale Li; Zizhen Liu; Wenxing Li; Hongqin Lyu; Jing Ye 001; Huawei Li 001; Xiaowei Li 001 (ITC-Asia, 2024)

Efficient Functional Safety Method for Gate-Level Fine-Grained Digital Circuits with ISO-26262. - Mingjun Wang; Hui Wang 152; Jianan Mu; Zizhen Liu; Jun Gao; Jing Ye 001; Huawei Li 001; Xiaowei Li 001 (ITC-Asia, 2024)

SPFL: A Self-Purified Federated Learning Method Against Poisoning Attacks. - Zizhen Liu; Weiyang He; Chip-Hong Chang; Jing Ye 001; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Inf. Forensics Secur., 2024)

ETPG: Efficient Transition Fault Simulation via Dual-Strategy Pattern Parallelism and Gate Restructuring. - Mingjun Wang; Hui Wang 152; Zizhen Liu; Feng Gu; Jianan Mu; Jiaping Tang; Jun Gao; Huawei Li 001; Jing Ye 001; Xiaowei Li 001 (ASP-DAC, 2025)

ERASER: Efficient RTL FAult Simulation Framework with Trimmed Execution Redundancy. - Jiaping Tang; Jianan Mu; Silin Liu; Zizhen Liu; Feng Gu; Xinyu Zhang; Leyan Wang; Shengwen Liang; Jing Ye 001; Huawei Li 001; Xiaowei Li 001 (DATE, 2025)

HighTPI: A Hierarchical Graph Based Intelligent Method for Test Point Insertion. - Zhiteng Chao; Bin Sun; Hongqin Lyu; Ge Yu; Minjun Wang; Wenxing Li; Zizhen Liu; Jianan Mu; Shengwen Liang; Jing Ye 001; Xiaowei Li 001; Huawei Li 001 (VTS, 2025)

A fast test compaction method using dedicated Pure MaxSAT solver embedded in DFT flow. - Zhiteng Chao; Xindi Zhang; Junying Huang; Zizhen Liu; Yixuan Zhao; Jing Ye 001; Shaowei Cai 001; Huawei Li 001; Xiaowei Li 001 (Integr., 2025)

ERASER: Efficient RTL FAult Simulation Framework with Trimmed Execution Redundancy. - Jiaping Tang; Jianan Mu; Silin Liu; Zizhen Liu; Feng Gu; Xinyu Zhang; Leyan Wang; Shenwen Liang; Jing Ye 001; Huawei Li 001; Xiaowei Li 001 (CoRR, 2025)

Extend IVerilog to Support Batch RTL Fault Simulation. - Jiaping Tang; Jianan Mu; Zizhen Liu; Zhiteng Chao; Jing Ye 001; Huawei Li 001 (CoRR, 2025)