Development of Multi-video Based Virtual Classroom and Its Application in English as Second Language Learning. - Ruimin Zhang; Bofeng Zhang; Jingchen Zhu; Huiting Huang (ISCSCT (1), 2008)

Fork Path: Batching ORAM Requests to Remove Redundant Memory Accesses. - Jingchen Zhu; Guangyu Sun 003; Xian Zhang 001; Chao Zhang 007; Weiqi Zhang; Yun Liang 001; Tao Wang 004; Yiran Chen 001; Jia Di (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

METRO: A Software-Hardware Co-Design of Interconnections for Spatial DNN Accelerators. - Zhao Wang; Guangyu Sun 003; Jingchen Zhu; Zhe Zhou 002; Yijiang Guo; Zhihang Yuan (CoRR, 2021)

FD-CNN: A Frequency-Domain FPGA Acceleration Scheme for CNN-Based Image-Processing Applications. - Xiaoyang Wang 006; Zhe Zhou 002; Zhihang Yuan; Jingchen Zhu; Yulong Cao; Yao Zhang; Kangrui Sun; Guangyu Sun 003 (ACM Trans. Embed. Comput. Syst., 2023)

Theseus: Towards High-Efficiency Wafer-Scale Chip Design Space Exploration for Large Language Models. - Jingchen Zhu; Chenhao Xue; Yiqi Chen; Zhao Wang; Guangyu Sun 003 (CoRR, 2024)

H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference. - Cong Li; Yihan Yin; Xintong Wu; Jingchen Zhu; Zhutianya Gao; Dimin Niu; Qiang Wu 012; Xin Si; Yuan Xie 001; Chen Zhang 001; Guangyu Sun 003 (ISCA, 2025)

AIM: Software and Hardware Co-design for Architecture-level IR-drop Mitigation in High-performance PIM. - Yuanpeng Zhang; Xing Hu 010; Xi Chen 107; Zhihang Yuan; Cong Li; Jingchen Zhu; Zhao Wang; Chenguang Zhang; Xin Si; Wei Gao; Qiang Wu 012; Runsheng Wang; et al. (ISCA, 2025)