On the Reliable Performance of Sequential Adders for Soft Computing. - Jinghang Liang; Jie Han 001; Fabrizio Lombardi (DFT, 2011)

Design and reliability analysis of multiple valued logic gates using carbon nanotube FETs. - Jinghang Liang; Jie Han 001; Linbin Chen; Fabrizio Lombardi (NANOARCH, 2012)

Stochastic Boolean networks: An efficient approach to modeling gene regulatory networks. - Jinghang Liang; Jie Han 001 (BMC Syst. Biol., 2012)

Analysis of Error Masking and Restoring Properties of Sequential Circuits. - Jinghang Liang; Jie Han 001; Fabrizio Lombardi (IEEE Trans. Computers, 2013)

New Metrics for the Reliability of Approximate and Probabilistic Adders. - Jinghang Liang; Jie Han 001; Fabrizio Lombardi (IEEE Trans. Computers, 2013)

A 6.0-13.5 GHz Alias-Locked Loop Frequency Synthesizer in 130 nm CMOS. - Jinghang Liang; Zhiyin Zhou; Jie Han 001; Duncan G. Elliott (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Gene perturbation and intervention in context-sensitive stochastic Boolean networks. - Peican Zhu; Jinghang Liang; Jie Han 001 (BMC Syst. Biol., 2014)

A Stochastic Computational Approach for Accurate and Efficient Reliability Evaluation. - Jie Han 001; Hao Chen; Jinghang Liang; Peican Zhu; Zhixi Yang; Fabrizio Lombardi (IEEE Trans. Computers, 2014)

Coresidual alias-locked loops. - Jinghang Liang; Duncan G. Elliott (ISCAS, 2016)

Frequency Synthesis Based on A Novel Differential Locking Mechanism. - Jinghang Liang; Duncan G. Elliott (ISCAS, 2018)