A low cost and high speed CSD-based symmetric transpose block FIR implementation. - Jinghao Ye; Youhua Shi; Nozomu Togawa; Masao Yanagisawa (ASICON, 2017)

A Bit-Segmented Adder Chain based Symmetric Transpose Two-Block FIR Design for High-Speed Signal Processing. - Jinghao Ye; Masao Yanagisawa; Youhua Shi (APCCAS, 2019)

A Zero-Gating Processing Element Design for Low-Power Deep Convolutional Neural Networks. - Lin Ye; Jinghao Ye; Masao Yanagisawa; Youhua Shi (APCCAS, 2019)

An Adder-Segmentation-based FIR for High Speed Signal Processing. - Jinghao Ye; Masao Yanagisawa; Youhua Shi (ASICON, 2019)

Static Error Analysis and Optimization of Faithfully Truncated Adders for Area-Power Efficient FIR Designs. - Jinghao Ye; Nozomu Togawa; Masao Yanagisawa; Youhua Shi (ISCAS, 2019)

A High-Performance Symmetric Hybrid Form Design for High-Order FIR Filters. - Jinghao Ye; Masao Yanagisawa; Youhua Shi (APCCAS, 2020)

Faithfully Truncated Adder-Based Area-Power Efficient FIR Design with Predefined Output Accuracy. - Jinghao Ye; Masao Yanagisawa; Youhua Shi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020)

Power-Efficient Deep Convolutional Neural Network Design Through Zero-Gating PEs and Partial-Sum Reuse Centric Dataflow. - Lin Ye; Jinghao Ye; Masao Yanagisawa; Youhua Shi (IEEE Access, 2021)