Lagrangian relaxation based topology synthesis for Application-Specific Network-on-Chips. - Jinglei Huang; Zhigang Li; Wei Zhong; Song Chen 001 (ASICON, 2015)

Floorplanning and Topology Synthesis for Application-Specific Network-on-Chips with RF-Interconnect. - Jinglei Huang; Song Chen 001; Wei Zhong; Wenchao Zhang; Shengxi Diao; Fujiang Lin (ACM Trans. Design Autom. Electr. Syst., 2016)

Integer linear programming based fault-tolerant topology synthesis for application-specific NoC. - Zhigang Li; Jinglei Huang; Qi Xu; Song Chen 001 (ASICON, 2017)

An Integrated Optimization Framework for Partitioning, Scheduling and Floorplanning on Partially Dynamically Reconfigurable FPGAs. - Xiaodong Xu; Qi Xu; Jinglei Huang; Song Chen 001 (ACM Great Lakes Symposium on VLSI, 2017)

Reconfigurable topology synthesis for application-specific noc on partially dynamically reconfigurable FPGAs. - Jinglei Huang; Xiaodong Xu; Lan Yao; Song Chen 001 (SLIP, 2017)

Integrated Optimization of Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems. - Song Chen 001; Jinglei Huang; Xiaodong Xu; Qi Xu (CoRR, 2018)

Lagrangian relaxation-based routing path allocation for application-specific network-on-chips. - Jinglei Huang; Wei Zhong; Zhigang Li; Song Chen 001 (Integr., 2018)

Reconfigurable topology synthesis for application-specific NoC on partially dynamically reconfigurable systems. - Jinglei Huang; Xiaodong Xu; Nan Wang 003; Song Chen 001 (Integr., 2019)

Generalized Fault-Tolerance Topology Generation for Application-Specific Network-on-Chips. - Song Chen 001; Mengke Ge; Zhigang Li; Jinglei Huang; Qi Xu; Feng Wu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Integrated Optimization of Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems. - Song Chen 001; Jinglei Huang; Xiaodong Xu; Bo Ding; Qi Xu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Solving slot allocation problem with multiple ATFM measures by using enhanced meta-heuristic algorithm. - Jing Tian; Xinchang Hao; Jibo Huang; Jinglei Huang; Mitsuo Gen (Comput. Ind. Eng., 2021)

Task modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems Based on Modern Heterogeneous FPGAs. - Bo Ding; Jinglei Huang; Junpeng Wang 002; Qi Xu; Song Chen 001; Yi Kang (CoRR, 2022)

Synthesizing Brain-network-inspired Interconnections for Large-scale Network-on-chips. - Mengke Ge; Xiaobing Ni; Qi Xu; Song Chen 001; Jinglei Huang; Yi Kang; Feng Wu 001 (ACM Trans. Design Autom. Electr. Syst., 2022)

Memory-aware Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems. - Bo Ding; Jinglei Huang; Qi Xu; Junpeng Wang 002; Song Chen 001; Yi Kang (ACM Trans. Design Autom. Electr. Syst., 2023)

Task Modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems with Heterogeneous Resources. - Bo Ding; Jinglei Huang; Junpeng Wang 002; Qi Xu; Song Chen 001; Yi Kang (ACM Trans. Design Autom. Electr. Syst., 2023)