Fast Timing Analysis of Transistor-Level Full Custom Digital Circuits. - Jingon Lee; Jinwook Jung; Youngsoo Shin (ISCAS, 2018)

Cut Optimization for Redundant Via Insertion in Self-Aligned Double Patterning. - Youngsoo Song; Daijoon Hyun; Jingon Lee; Jinwook Jung; Youngsoo Shin (ACM Trans. Design Autom. Electr. Syst., 2019)