A field programmable transistor array featuring single-cycle partial/full dynamic reconfiguration. - Jingxiang Tian; Gaurav Rajavendra Reddy; Jiajia Wang; William Swartz; Yiorgos Makris; Carl Sechen (DATE, 2017)

Design Obfuscation through Selective Post-Fabrication Transistor-Level Programming. - Mustafa M. Shihab; Jingxiang Tian; Gaurav Rajavendra Reddy; Bo Hu; William Swartz; Benjamin Carrión Schäfer; Carl Sechen; Yiorgos Makris (DATE, 2019)

Functional Obfuscation of Hardware Accelerators through Selective Partial Design Extraction onto an Embedded FPGA. - Bo Hu; Jingxiang Tian; Mustafa M. Shihab; Gaurav Rajavendra Reddy; William Swartz; Yiorgos Makris; Benjamin Carrión Schäfer; Carl Sechen (ACM Great Lakes Symposium on VLSI, 2019)

CASPER: CAD Framework for a Novel Transistor-Level Programmable Fabric. - Mustafa M. Shihab; Bharath Ramanidharan; Gaurav Rajavendra Reddy; Jingxiang Tian; William Swartz; Carl Sechen; Yiorgos Makris (ISCAS, 2020)

ATTEST: Application-Agnostic Testing of a Novel Transistor-Level Programmable Fabric. - Mustafa Munawar Shihab; Bharath Ramanidharan; Suraag Sunil Tellakula; Gaurav Rajavendra Reddy; Jingxiang Tian; Carl Sechen; Yiorgos Makris (VTS, 2020)