A 1-16 Gb/s All-Digital Clock and Data Recovery With a Wideband High-Linearity Phase Interpolator. - Guoying Wu; Deping Huang; Jingxiao Li; Ping Gui; Tianwei Liu; Shita Guo; Rui Wang 035; Yanli Fan; Sudipto Chakraborty; Mark Morgan (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Accurate Formulation of the Skin and Proximity Effects in High-Speed Cable System. - Oussama Gassab; Yanning Chen; Yali Shao; Jingxiao Li; Ding-E. Wen; Fang He; Zhizhen Su; Peina Zhong; Jian Wang 131; Dongyan Zhao 002; Wen-Yan Yin (IEEE Access, 2022)

Adaptive DSR routing caching strategy based on local connection mechanism. - Zenyu Cai; Jingxiao Li; Yuhao Zhang; Jianwei Zhang; Wenqian Wang (Int. J. Embed. Syst., 2022)