A novel and efficient timing-driven global router for standard cell layout design based on critical network concept. - Tong Jing; Xianlong Hong; Haiyun Bao; Yici Cai; Jingyu Xu 001; Jun Gu (ISCAS (1), 2002)

UTACO: a unified timing and congestion optimizing algorithm for standard cell global routing. - Tong Jing; Xianlong Hong; Haiyun Bao; Yici Cai; Jingyu Xu 001; Chung-Kuan Cheng; Jun Gu (ASP-DAC, 2003)

A Novel Timing-Driven Global Routing Algorithm Considering Coupling Effects for High Performance Circuit Design. - Jingyu Xu 001; Xianlong Hong; Tong Jing; Yici Cai; Jun Gu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

An efficient hierarchical timing-driven Steiner tree algorithm for global routing. - Jingyu Xu 001; Xianlong Hong; Tong Jing; Yici Cai; Jun Gu (Integr., 2003)

CNB: A Critical-Network-Based Timing Optimization Method for Standard Cell Global Routing. - Xianlong Hong; Tong Jing; Jingyu Xu 001; Haiyun Bao; Jun Gu (J. Comput. Sci. Technol., 2003)

SSTT: Efficient Local Search for GSI Global Routing. - Tong Jing; Xianlong Hong; Haiyun Bao; Jingyu Xu 001; Jun Gu (J. Comput. Sci. Technol., 2003)

Performance and RLC crosstalk driven global routing. - Ling Zhang; Tong Jing; Xianlong Hong; Jingyu Xu 001; Jinjun Xiong; Lei He 001 (ISCAS (5), 2004)

UTACO: a unified timing and congestion optimization algorithm for standard cell global routing. - Tong Jing; Xianlong Hong; Jingyu Xu 001; Haiyun Bao; Chung-Kuan Cheng; Jun Gu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem. - Tong Jing; Ling Zhang; Jinghong Liang; Jingyu Xu 001; Xianlong Hong; Jinjun Xiong; Lei He 001 (ASP-DAC, 2005)

Obstacle-Avoiding Rectilinear Minimum-Delay Steiner Tree Construction towards IP-Block-Based SOC Design. - Jingyu Xu 001; Xianlong Hong; Tong Jing; Yang Yang 040 (ISQED, 2005)

Timing-Driven Global Routing with Efficient Buffer Insertion. - Jingyu Xu 001; Xianlong Hong; Tong Jing (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

A coupling and crosstalk-considered timing-driven global routing algorithm for high-performance circuit design. - Jingyu Xu 001; Xianlong Hong; Tong Jing; Ling Zhang; Jun Gu (Integr., 2006)

Obstacle-avoiding rectilinear minimum-delay Steiner tree construction toward IP-block-based SOC design. - Jingyu Xu 001; Xianlong Hong; Tong Jing; Yang Yang 040 (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

Efficient range pattern matching algorithm for process-hotspot detection. - Hailong Yao; Subarna Sinha; Jingyu Xu 001; Charles C. Chiang; Yici Cai; Xianlong Hong (IET Circuits Devices Syst., 2008)