One chip-low power digital-TCXO with sub-ppm accuracy. - Se-Joong Lee; Jinho Han; Seung-Ho Hank; Joe-Ho Lee; Jung-Su Kim; Minkyu Je; Hoi-Jun Yoo (ISCAS, 2000)

Analysis of a Frequency Acquisition Technique With a Stochastic Reference Clock Generator. - Jinho Han; Jaehyeok Yang; Hyeon-Min Bae (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

0.6-2.7-Gb/s Referenceless Parallel CDR With a Stochastic Dispersion-Tolerant Frequency Acquisition Technique. - Jinho Han; Hyosup Won; Hyeon-Min Bae (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A 0.87 W Transceiver IC for 100 Gigabit Ethernet in 40 nm CMOS. - Hyosup Won; Taehun Yoon; Jinho Han; Joon-Yeong Lee; Jong-Hyeok Yoon; Taeho Kim; Jeong-Sup Lee; Sangeun Lee; Kwangseok Han; Jinhee Lee; Jinho Park 006; Hyeon-Min Bae (IEEE J. Solid State Circuits, 2015)

A Fault-Tolerant Cache System of Automotive Vision Processor Complying With ISO26262. - Jinho Han; Youngsu Kwon; Kyeongjin Byun; Hoi-Jun Yoo (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

A 4×10-Gb/s Referenceless-and-Masterless Phase Rotator-Based Parallel Transceiver in 90-nm CMOS. - Joon-Yeong Lee; Jaehyeok Yang; Jong-Hyeok Yoon; Soon-Won Kwon; Hyosup Won; Jinho Han; Hyeon-Min Bae (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A 1GHz fault tolerant processor with dynamic lockstep and self-recovering cache for ADAS SoC complying with ISO26262 in automotive electronics. - Jinho Han; Youngsu Kwon; Yong Cheol Peter Cho; Hoi-Jun Yoo (A-SSCC, 2017)

A 103.125-Gb/s Reverse Gearbox IC in 40-nm CMOS for Supporting Legacy 10- and 40-GbE Links. - Taehun Yoon; Joon-Yeong Lee; Jinhee Lee; Kwangseok Han; Jeong-Sup Lee; Sangeun Lee; Taeho Kim; Jinho Han; Hyosup Won; Jinho Park 006; Hyeon-Min Bae (IEEE J. Solid State Circuits, 2017)

Function-Safe Vehicular AI Processor with Nano Core-In-Memory Architecture. - Youngsu Kwon; Jeongmin Yang; Yong Cheol Peter Cho; Kyoung-Seon Shin; Jaehoon Chung; Jinho Han; Chun-Gi Lyuh; Hyun-Mi Kim; Chan Kim; Min-Seok Choi (AICAS, 2019)

Implementation of Yolo-v2 Image Recognition and Other Testbenches for a CNN Accelerator. - Chan Kim; In San Jeon; Young-Su Kwon; Hyun-Mi Kim; Chun-Gi Lyuh; Yong Cheol Peter Cho; Jeongmin Yang; Jaehoon Chung; Kyoung-Seon Shin; Jinho Han; Min-Seok Choi (ICCE-Berlin, 2019)

AI 32TFLOPS Autonomous Driving Processor on AI-Ware with Adaptive Power Saving. - Youngsu Kwon; Yong Cheol Peter Cho; Jeongmin Yang; Jaehoon Chung; Kyoung-Seon Shin; Jinho Han; Chan Kim; Chun-Gi Lyuh; Hyun-Mi Kim; In San Jeon; Min-Seok Choi (ISOCC, 2019)

HPC LINPACK Parameter Optimization on Homo-/Heterogeneous System of ARM Neoverse N1SDP. - Je-Seok Ham; Yong Cheol Peter Cho; Ju-Yeob Kim; Chun-Gi Lyuh; Jin-Kyu Kim; Jinho Han; Youngsu Kwon (HPC Asia, 2021)

Live Demonstration: A Neural Processor for AI Acceleration. - Hyeji Kim; Jaehoon Chung; Kyoung-Seon Shin; Chun-Gi Lyuh; Hyun-Mi Kim; Chan Kim; Yong Cheol Peter Cho; Jeongmin Yang; Je-Seok Ham; Minseok Choi; Jinho Han; Youngsu Kwon (ISCAS, 2021)

ArtBrain-K: AI Processor based-on 5-PetaFLOPS AI Server System. - Jinho Han; Chun-Gi Lyuh; Kyeongsun Shin; Hyun-Mi Kim; Hyunjeong Kwon; Jaehoon Chung; Yong Cheol Peter Cho; Jinkyu Kim; Jeonghui Suk; Chan Kim; Minseok Choi; Youngsu Kwon (AICAS, 2022)

M3FPU: Multiformat Matrix Multiplication FPU Architectures for Neural Network Computations. - Won Jeon; Yong Cheol Peter Cho; Hyun-Mi Kim; Hyeji Kim; Jaehoon Chung; Ju-Yeob Kim; Miyoung Lee; Chun-Gi Lyuh; Jinho Han; Youngsu Kwon (AICAS, 2022)

AIWareK: Compiling PyTorch Model for AI Processor Using MLIR Framework. - Hyunjeong Kwon; Hyun-Mi Kim; Chun-Gi Lyuh; Jin-Kyu Kim; Jinho Han; Youngsu Kwon (AICAS, 2022)

Backward Graph Construction and Lowering in DL Compiler for Model Training on AI Accelerators. - Hyunjeong Kwon; Youngsu Kwon; Jinho Han (ISOCC, 2022)

Chiplet Heterogeneous-Integration AI Processor. - Youngsu Kwon; Jinho Han; Yong Cheol Peter Cho; Juyeob Kim; Jaehoon Chung; Jaewoong Choi; Sujin Park; Igyeong Kim; Hyunjeong Kwon; Jinkyu Kim; Hyunmi Kim; Won Jeon; et al. (ICEIC, 2023)

2.5D Large-Scale Interposer Bonding Process Verification using Daisy-Chain for PIM Heterogeneous Integration Platform. - Sujin Park; Yi-Gyeong Kim; Young-Deuk Jeon; Min-Hyung Cho; Jinho Han; Youngsu Kwon (ICEIC, 2023)

DQ and DQS Receiver for HBM3 Memory Interface with DFE Offset Calibration. - Sujin Park; Young-Deuk Jeon; Yi-Gyeong Kim; Min-Hyung Cho; Jinho Han; Jaehoon Chung; Jaewoong Choi; Youngsu Kwon (ISOCC, 2023)

A 6.4Gb/s/pin HBM3 Digital PHY with Low-Power, Area-Efficient Techniques for Chiplet-Based AI processors in 12-nm CMOS. - Jaewoong Choi; Yi-Gyeong Kim; Juyeob Kim; Jaehoon Chung; Young-Deuk Jeon; Min-Hyung Cho; Sujin Park; Jinho Han (A-SSCC, 2024)