Bit Parallel 6T SRAM In-memory Computing with Reconfigurable Bit-Precision. - Kyeongho Lee; Jinho Jeong 002; Sungsoo Cheon; Woong Choi; Jongsun Park 001 (DAC, 2020)

Fast 6T SRAM Bit-Line Computing with Consecutive Short Pulse Word-Lines and Skewed Inverter. - Jinho Jeong 002; Jongsun Park 001 (ISOCC, 2020)

An Even/Odd Error Detection Based Low-Complexity Chase Decoding for Low-Latency RS Decoder Design. - Jinho Jeong 002; Dongyeob Shin; Wongyu Shin; Jongsun Park 001 (IEEE Commun. Lett., 2021)