Parasitic-aware design and optimization of a fully integrated CMOS wideband amplifier. - Jinho Park 006; Kiyong Choi; David J. Allstot (ASP-DAC, 2003)

RF circuit synthesis using particle swarm optimization. - Jinho Park 006; David J. Allstot (ISCAS (5), 2004)

A 12.5 GHz RF matrix amplifier in 180nm SOI CMOS. - Jinho Park 006; David J. Allstot (ISCAS (1), 2004)

Parasitic-aware RF circuit design and optimization. - Jinho Park 006; Kiyong Choi; David J. Allstot (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)

A full-range all-pass variable phase shifter for multiple antenna receivers. - Hossein Zarei; Allan Ecker; Jinho Park 006; David J. Allstot (ISCAS (3), 2005)

A matrix amplifier in 0.18-μm SOI CMOS. - Jinho Park 006; David J. Allstot (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

A power-and-area efficient 10 × 10 Gb/s bootstrap transceiver in 40 nm CMOS for reference-less and lane-independent operation. - Joon-Yeong Lee; Kwangseok Han; Taeho Kim; Sangeun Lee; Jeong-Sup Lee; Taehun Yoon; Jinho Park 006; Hyeon-Min Bae (CICC, 2015)

An on-chip stochastic sigma-tracking eye-opening monitor for BER-optimal adaptive equalization. - Hyosup Won; Kwangseok Han; Sangeun Lee; Jinho Park 006; Hyeon-Min Bae (CICC, 2015)

A 100-GbE reverse gearbox IC in 40nm CMOS for supporting legacy 10- and 40-GbE standards. - Taehun Yoon; Joon-Yeong Lee; Kwangseok Han; Jeong-Sup Lee; Sangeun Lee; Taeho Kim; Hyosup Won; Jinho Park 006; Hyeon-Min Bae (VLSIC, 2015)

A 0.87 W Transceiver IC for 100 Gigabit Ethernet in 40 nm CMOS. - Hyosup Won; Taehun Yoon; Jinho Han; Joon-Yeong Lee; Jong-Hyeok Yoon; Taeho Kim; Jeong-Sup Lee; Sangeun Lee; Kwangseok Han; Jinhee Lee; Jinho Park 006; Hyeon-Min Bae (IEEE J. Solid State Circuits, 2015)

An Automatic Loop Gain Control Algorithm for Bang-Bang CDRs. - Soon-Won Kwon; Joon-Yeong Lee; Jinhee Lee; Kwangseok Han; Taeho Kim; Sangeun Lee; Jeong-Sup Lee; Taehun Yoon; Hyosup Won; Jinho Park 006; Hyeon-Min Bae (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A Power-and-Area Efficient 10 × 10 Gb/s Bootstrap Transceiver in 40 nm CMOS for Referenceless and Lane-Independent Operation. - Joon-Yeong Lee; Kwangseok Han; Taehun Yoon; Taeho Kim; Sangeun Lee; Jeong-Sup Lee; Jinho Park 006; Hyeon-Min Bae (IEEE J. Solid State Circuits, 2016)

A 103.125-Gb/s Reverse Gearbox IC in 40-nm CMOS for Supporting Legacy 10- and 40-GbE Links. - Taehun Yoon; Joon-Yeong Lee; Jinhee Lee; Kwangseok Han; Jeong-Sup Lee; Sangeun Lee; Taeho Kim; Jinho Han; Hyosup Won; Jinho Park 006; Hyeon-Min Bae (IEEE J. Solid State Circuits, 2017)

A 28-Gb/s Receiver With Self-contained Adaptive Equalization and Sampling Point Control Using Stochastic Sigma-Tracking Eye-Opening Monitor. - Hyosup Won; Joon-Yeong Lee; Taehun Yoon; Kwangseok Han; Sangeun Lee; Jinho Park 006; Hyeon-Min Bae (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A 25.78125Gbps Bi-directional Transceiver with Framed-Pulsewidth Modulation (FPWM) for Extended Reach Optical Links in 28nm CMOS. - Woohyun Kwon; Hyosup Won; Taeho Kim; Ha-Il Song; Hanho Choi; Sejun Jeon; Soon-Won Kwon; Huxian Jin; Jun-Gi Jo; Tai Young Kim; Jake Eu; Jinho Park 006; et al. (VLSI Technology and Circuits, 2022)

A 26-Gb/s Framed-Pulsewidth Modulation Transceiver for Extended Reach Optical Links. - Woohyun Kwon; Hyosup Won; Taeho Kim; Sejun Jeon; Soon-Won Kwon; Ha-Il Song; Hanho Choi; Bongjin Kim; Huxian Jin; Jun-Gi Jo; Woosang Han; Tai-Young Kim; et al. (IEEE J. Solid State Circuits, 2024)