Presence Attestation: The Missing Link in Dynamic Trust Bootstrapping. - Zhangkai Zhang; Xuhua Ding; Gene Tsudik; Jinhua Cui 002; Zhoujun Li 001 (CCS, 2017)

H-Securebox: A Hardened Memory Data Protection Framework on ARM Devices. - Zhangkai Zhang; Zhoujun Li 001; Chunhe Xia; Jinhua Cui 002; Jinxin Ma (DSC, 2018)

A Distributed Storage System for Robust, Privacy-Preserving Surveillance Cameras. - Jiaping Yu; Haiwen Chen; Kui Wu 001; Zhiping Cai; Jinhua Cui 002 (ICDCS, 2020)

Binary Compatibility For SGX Enclaves. - Shweta Shinde; Jinhua Cui 002; Satyaki Sen; Pinghai Yuan; Prateek Saxena (CoRR, 2020)

SmashEx: Smashing SGX Enclaves Using Exceptions. - Jinhua Cui 002; Jason Zhijingcheng Yu; Shweta Shinde; Prateek Saxena; Zhiping Cai (CCS, 2021)

TSAEns: Ensemble Learning for KPI Anomaly Detection. - Chengyu Wang 008; Tao Yang 041; Jinhua Cui 002; Yu Li; Tongqing Zhou; Zhiping Cai (ICA3PP (1), 2021)

Leveraging blockchain for cross-institution data sharing and authentication in mobile healthcare. - Le Lai; Tongqing Zhou; Zhiping Cai; Jiaping Yu; Hao Bai; Jinhua Cui 002 (MSN, 2021)

Dynamic Binary Translation for SGX Enclaves. - Jinhua Cui 002; Shweta Shinde; Satyaki Sen; Prateek Saxena; Pinghai Yuan (ACM Trans. Priv. Secur., 2022)

A Comparison Study of the Compatibility Approaches for SGX Enclaves. - Jinhua Cui 002; Yiyun Yin; Zhiping Cai; Jiliang Zhang 002 (ATS, 2023)

Spoiler-Alert: Detecting Spoiler Attacks Using a Cuckoo Filter. - Jinhua Cui 002; Yiyun Yin; Congcong Chen; Jiliang Zhang 002 (DATE, 2023)

SYNC+SYNC: Software Cache Write Covert Channels Exploiting Memory-disk Synchronization. - Congcong Chen; Jinhua Cui 002; Gang Qu 001; Jiliang Zhang 002 (CoRR, 2023)

BETA: Automated Black-box Exploration for Timing Attacks in Processors. - Congcong Chen; Jinhua Cui 002; Jiliang Zhang 002 (CoRR, 2024)

Write+Sync: Software Cache Write Covert Channels Exploiting Memory-Disk Synchronization. - Congcong Chen; Jinhua Cui 002; Gang Qu 001; Jiliang Zhang 002 (IEEE Trans. Inf. Forensics Secur., 2024)

Timing Side-channel Attacks and Countermeasures in CPU Microarchitectures. - Jiliang Zhang 002; Congcong Chen; Jinhua Cui 002; Keqin Li 001 (ACM Comput. Surv., 2024)

CPU Address-Leakage Transient Execution Attack Detection and Its Countermeasures. - Yiyun Yin; Jinhua Cui 002; Jiliang Zhang 002 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)