A 8.9 to 10-GHz -97.86-dBc Reference Spur Pulser-Free Continuous Charge Pump Sub-Sampling PLL With Fine-Tunable Dead-Zone Generator in 65-nm CMOS Process. - Sangwon Kim; Kihoon Kwon; Minseo Park; Jinhyuk Ahn; Junseo Kim; Joonho Gil; Chulhyun Park; Yunseong Eo; Ramesh Harjani; Taehyoun Oh (IEEE Access, 2025)

A DTC-Based Snapshot ADPLL With Feedforward Fractional Spur Cancellation and Asynchronous Duty-Modulation Dithering DCO Achieving-71.6 dBc Fractional Spur in 65-nm CMOS Process. - Kihoon Kwon; Sangwon Kim; Minseo Park; Jinhyuk Ahn; Gahyeon Lee; Joonho Gil; Chulhyun Park; Yunseong Eo; Hyungkyu Choi; Chulho Kang; Eun Seong Kim; Nam-Young Kim; et al. (IEEE Access, 2026)