VIDE: a visual VHDL integrated design environment. - Jinian Bian; Hongxi Xue; Ming Su (ASP-DAC, 1997)

FSM Modeling of Synchronous VHDL Design for Symbolic Model Checking. - Jinsong Bei; Hongxing Li; Jinian Bian; Hongxi Xue; Xianlong Hong (ASP-DAC, 1999)

IBAW: an implication-tree based alternative-wiring logic transformation algorithm. - Wangning Long; Yu-Liang Wu; Jinian Bian (ASP-DAC, 2000)

Accelerating Logic Rewiring Using Implication Analysis Tree. - Chin Ngai Sze; Wangning Long; Yu-Liang Wu; Jinian Bian (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Property Classification for Functional Verification Based. - Ming Zhu; Jinian Bian; Weimin Wu; Hongxi Xue (Asian Test Symposium, 2003)

PFGASAT- A Genetic SAT Solver Combining Partitioning and Fuzzy Strategie. - Jianzhou Zhao; Jinian Bian; Weimin Wu (COMPSAC, 2004)

CA-Ex: A Tuning-Incremental Methodology for Communication Architectures in Embedded Systems. - Haili Wang; Jinian Bian; Yawen Niu; Kun Tong; Yunfeng Wang (ICESS, 2004)

A Distributed Architecture Model for Heterogeneous Multiprocessor System-on-Chip Design. - Qiang Wu; Jinian Bian; Hongxi Xue (ICESS, 2004)

Model Optimization Techniques in a Verification Platform for Classified Properties. - Ming Zhu; Jinian Bian; Weimin Wu (ICESS, 2004)

System-level architectural exploration using allocation-on-demand technique. - Qiang Wu; Jinian Bian; Hongxi Xue (ASP-DAC, 2005)

iTuCoMe: HCDFG-based incremental tuning HW/SW co-design methodology for multi-level exploration. - Haili Wang; Jinian Bian; Qiang Wu; Yunfeng Wang (CSCWD (2), 2005)

Cooperation of SMV and Jeda for the property checking of mixed control and data intensive designs. - Jianzhou Zhao; Jinian Bian; Weimin Wu (CSCWD (2), 2005)

HW/SW Interface Synthesis Based on Avalon Bus Specification for Nios-Oriented SoC Design. - Feng Lin; Haili Wang; Jinian Bian (FPT, 2005)

A New Methodology of Integrating High Level Synthesis and Floorplan for SoC Design. - Yunfeng Wang; Jinian Bian; Xianlong Hong; Liu Yang; Qiang Zhou 001; Qiang Wu (ICESS, 2005)

A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation. - Zhuoyuan Li 003; Xianlong Hong; Qiang Zhou 001; Yici Cai; Jinian Bian; Hannal Yang; Prashant Saxena; Vijay Pitchumani (ISCAS (6), 2005)

Interconnect delay optimization via high level re-synthesis after floorplanning. - Yunfeng Wang; Jinian Bian; Xianlong Hong (ISCAS (6), 2005)

A Clustering ILP Model for Fast Instruction Selection in Embedded Applicated Specific Processor Design. - Kang Zhao; Jinian Bian (APCCAS, 2006)

High Level Synthesis with Multiple supply Voltages for Energy and Combined Peak Power Minimization. - Zhen Zhao; Jinian Bian; Zhipeng Liu; Yunfeng Wang; Kang Zhao (APCCAS, 2006)

From Software to Hardware - A Novel TLM Auto-Generating Method. - Liang Zhu; Jinian Bian (APCCAS, 2006)

Cooperative Bounded Model Checking Using STE and Hybrid Three-Valued SAT Solving. - Shujun Deng; Weimin Wu; Jinian Bian (CSCWD, 2006)

Bounded Model Checking Combining Symbolic Trajectory Evaluation Abstraction with Hybrid Three-Valued SAT Solving. - Shujun Deng; Weimin Wu; Jinian Bian (CSCWD (Selected Papers), 2006)

An Efficient Cooperative Design Framework for SOC On-Chip Communication Architecture System-Level Design. - Yawen Niu; Jinian Bian; Haili Wang; Kun Tong (CSCWD (Selected Papers), 2006)

AGOM: A Novel Method of Embedded System Communication Architecture Design in System Level Design. - Yawen Niu; Jinian Bian; Haili Wang; Kun Tong; Liang Zhu (CSCWD, 2006)

Universal data model platform: the data-centric evolution for system level codesign. - Kun Tong; Jinian Bian; Haili Wang (CSCWD, 2006)

Integrating dynamic thermal via planning with 3D floorplanning algorithm. - Zhuoyuan Li 003; Xianlong Hong; Qiang Zhou 001; Shan Zeng; Jinian Bian; Hannah Honghua Yang; Vijay Pitchumani; Chung-Kuan Cheng (ISPD, 2006)

A Heterogeneous Dependency Graph as Intermediate Representation for Instruction Set Customization. - Kang Zhao; Jinian Bian; Sheqin Dong (JCIS, 2006)

A novel collaborative scheme of simulation and model checking for system properties verification. - Ming Zhu; Jinian Bian; Weimin Wu (Comput. Ind., 2006)

Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization. - Zhuoyuan Li 003; Xianlong Hong; Qiang Zhou 001; Yici Cai; Jinian Bian; Hannah Honghua Yang; Vijay Pitchumani; Chung-Kuan Cheng (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration. - Zhuoyuan Li 003; Xianlong Hong; Qiang Zhou 001; Jinian Bian; Hannah Honghua Yang; Vijay Pitchumani (ACM Trans. Design Autom. Electr. Syst., 2006)

EHSAT Modeling from Algorithm Description for RTL Model Checking. - Xiaoqing Yang; Jinian Bian; Shujun Deng; Yanni Zhao (ATS, 2007)

Power-driven Real-time System Design with Energy Efficiency via ISA Customization. - Chenqian Jiang; Jinian Bian; Kang Zhao (CAD/Graphics, 2007)

VPH: Versatile Routability-Driven Place Algorithm for Hierarchical FPGAs Based on VPR. - Yanhua Wang; Qiang Zhou 001; Jinian Bian; Junhua Qu (CAD/Graphics, 2007)

A Management System of Metropolis Energy Information. - Hui Zhang; Jinian Bian (CSCWD, 2007)

A Fast Custom Instructions Identification Algorithm based on Basic Convex Pattern Model for Supporting ASIP Automated Design. - Kang Zhao; Jinian Bian; Sheqin Dong (CSCWD, 2007)

EHSAT: An Efficient RTL Satisfiability Solver Using an Extended DPLL Procedure. - Shujun Deng; Jinian Bian; Weimin Wu; Xiaoqing Yang; Yanni Zhao (DAC, 2007)

An effective buffer planning algorithm for IP based fixed-outline SOC placement. - Ou He; Sheqin Dong; Jinian Bian; Yuchun Ma; Xianlong Hong (ACM Great Lakes Symposium on VLSI, 2007)

Interconnect Delay and Power Optimization by Module Duplication for Integration of High Level Synthesis and Floorplan. - Zhipeng Liu; Jinian Bian; Qiang Zhou 001; Hui Dai (ISVLSI, 2007)

Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning. - Zhuoyuan Li 003; Xianlong Hong; Qiang Zhou 001; Shan Zeng; Jinian Bian; Wenjian Yu; Hannah Honghua Yang; Vijay Pitchumani; Chung-Kuan Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Low power clock buffer planning methodology in F-D placement for large scale circuit design. - Yanfeng Wang; Qiang Zhou 001; Yici Cai; Jiang Hu; Xianlong Hong; Jinian Bian (ASP-DAC, 2008)

Cache miss reduction through hardware-assisted loop optimization. - Kang Zhao; Jinian Bian; Chenqian Jiang; Sheqin Dong; Satoshi Goto (CSCWD, 2008)

MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation. - Xing Wei; Juanjuan Chen; Qiang Zhou 001; Yici Cai; Jinian Bian; Xianlong Hong (FPL, 2008)

HyMacs: hybrid memory access optimization based on custom-instruction scheduling. - Kang Zhao; Jinian Bian; Sheqin Dong; Yang Song 002; Satoshi Goto (ACM Great Lakes Symposium on VLSI, 2008)

A novel fixed-outline floorplanner with zero deadspace for hierarchical design. - Ou He; Sheqin Dong; Jinian Bian; Satoshi Goto; Chung-Kuan Cheng (ICCAD, 2008)

Automated Specific Instruction Customization Methodology for Multimedia Processor Acceleration. - Kang Zhao; Jinian Bian; Sheqin Dong; Yang Song 002; Satoshi Goto (ISQED, 2008)

A cooperative universal data model platform for the data-centric electronic system-level design. - Kun Tong; Jinian Bian; Haili Wang (Adv. Eng. Informatics, 2008)

Fast Custom Instruction Identification Algorithm Based on Basic Convex Pattern Model for Supporting ASIP Automated Design. - Kang Zhao; Jinian Bian; Sheqin Dong; Yang Song 002; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Exploring Partitions Based on Search Space Smoothing for Heterogeneous Multiprocessor System. - Kang Zhao; Jinian Bian; Sheqin Dong; Yang Song 002; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Self-adjusting constrained random stimulus generation using splitting evenness evaluation and XOR constraints. - Shujun Deng; Zhiqiu Kong; Jinian Bian; Yanni Zhao (ASP-DAC, 2009)

Peak temperature control in thermal-aware behavioral synthesis through allocating the number of resources. - Junbo Yu; Qiang Zhou 001; Jinian Bian (ASP-DAC, 2009)

An approach to synthesis delay semantics in VHDL. - Lixin Cheng; Jinian Bian; Yunyun Liu (CAD/Graphics, 2009)

Fast placement for large-scale hierarchical FPGAs. - Hui Dai; Qiang Zhou 001; Yici Cai; Jinian Bian; Xianlong Hong (CAD/Graphics, 2009)

Global density smoothing technique for analytical placement algorithm. - Dawei Liu; Qiang Zhou 001; Jinian Bian; Yanming Jia (CAD/Graphics, 2009)

Random stimulus generation with self-tuning. - Yanni Zhao; Jinian Bian; Shujun Deng; Zhiqiu Kong (CSCWD, 2009)

Cell shifting aware of wirelength and overlap. - Dawei Liu; Qiang Zhou 001; Jinian Bian; Yici Cai; Xianlong Hong (ISQED, 2009)

Peak Temperature Reduction by Physical Information Driven Behavioral Synthesis with Resource Usage Allocation. - Junbo Yu; Qiang Zhou 001; Gang Qu 001; Jinian Bian (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Constrained Stimulus Generation with Self-Adjusting Using Tabu Search with Memory. - Yanni Zhao; Jinian Bian; Shujun Deng; Zhiqiu Kong; Kang Zhao (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Pipeline-Based Partition Exploration for Heterogeneous Multiprocessor Synthesis. - Kang Zhao; Jinian Bian; Sheqin Dong; Yang Song 002; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Peeling algorithm for custom instruction identification. - Kang Zhao; Jinian Bian (APCCAS, 2010)

An architecture-aware routing optimization via satisfiabilty for hierarchical FPGA. - Limin Zhu; Qiang Zhou 001; Yici Cai; Jinian Bian (CSCWD, 2010)

Behavioral level dual-vth design for reduced leakage power with thermal awareness. - Junbo Yu; Qiang Zhou 001; Gang Qu 001; Jinian Bian (DATE, 2010)

Bus via reduction based on floorplan revising. - Ou He; Sheqin Dong; Jinian Bian; Satoshi Goto; Chung-Kuan Cheng (ACM Great Lakes Symposium on VLSI, 2010)

Wirelength-driven force-directed 3D FPGA placement. - Wentao Sui; Sheqin Dong; Jinian Bian (ACM Great Lakes Symposium on VLSI, 2010)

A low power clock network placement framework. - Dawei Liu; Qiang Zhou 001; Yongqiang Lu 001; Jinian Bian (ISQED, 2010)

Mutation-based diagnostic test generation for hardware design error diagnosis. - Shujun Deng; Kwang-Ting Cheng; Jinian Bian; Zhiqiu Kong (ITC, 2010)

Multilevel Optimization for Large-Scale Hierarchical FPGA Placement. - Hui Dai; Qiang Zhou 001; Jinian Bian (J. Comput. Sci. Technol., 2010)

Pruning-based trace signal selection algorithm. - Kang Zhao; Jinian Bian (ASP-DAC, 2011)

Instruction-level hardware/software partition through DFG exploration. - Kang Zhao; Jinian Bian (CSCWD, 2011)

A fast recursive detailed routing algorithm for hierarchical FPGAs. - Limin Zhu; Jinian Bian; Qiang Zhou 001; Yici Cai (CSCWD, 2011)

Processor Accelerator Customization through Data Flow Graph Exploration. - Kang Zhao; Jinian Bian (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

Buffer Planning for IP Placement Using Sliced-LFF. - Ou He; Sheqin Dong; Jinian Bian; Satoshi Goto (VLSI Design, 2011)

PDPR: Fine-Grained Placement for Dynamic Partially Reconfigurable FPGAs. - Ruining He; Guoqiang Liang; Yuchun Ma; Yu Wang 002; Jinian Bian (ARC, 2012)

ISBA: An independent set-based algorithm for automated partial reconfiguration module generation. - Ruining He; Yuchun Ma; Kang Zhao; Jinian Bian (ICCAD, 2012)

RAW Introduction. - Jürgen Becker 001; Jinian Bian; Christophe Bobda; René Cumplido; Michael Hübner 001 (IPDPS Workshops, 2012)

SMPP: Generic SAT Solver over Reconfigurable Hardware Accelerator. - Zhongda Yuan; Yuchun Ma; Jinian Bian (IPDPS Workshops, 2012)

Pruning-Based Trace Signal Selection Algorithm for Data Acquisition in Post-Silicon Validation. - Kang Zhao; Jinian Bian (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

UNISM: Unified Scheduling and Mapping for General Networks on Chip. - Ou He; Sheqin Dong; Wooyoung Jang; Jinian Bian; David Z. Pan (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Incremental 3D NoC synthesis based on physical-aware router merging algorithm. - Yuanyuan Li; Ning Xu 006; Yuchun Ma; Jinian Bian (ASICON, 2013)

Data dependency aware prefetch scheduling for Dynamic Partial reconfigurable designs. - Jixin Zhang; Ning Xu 006; Yuchun Ma; Yu Wang 002; Jinian Bian (ASICON, 2013)

Efficient custom instruction generation based on characterizing of basic blocks. - Guoqiang Liang; Yuchun Ma; Kang Zhao; Jinian Bian (CSCWD, 2013)

Automatic enhanced CDFG generation based on runtime instrumentation. - Zhongda Yuan; Yuchun Ma; Jinian Bian; Kang Zhao (CSCWD, 2013)

Binding Hardware IPs to Specific FPGA Device via Inter-twining the PUF Response with the FSM of Sequential Circuits. - Jiliang Zhang 002; Yaping Lin; Yongqiang Lu 001; Ray C. C. Cheung; Wenjie Che; Qiang Zhou 001; Jinian Bian (FCCM, 2013)

FPGA IP protection by binding Finite State Machine to Physical Unclonable Function. - Jiliang Zhang 002; Yaping Lin; Yongqiang Lyu 001; Gang Qu 001; Ray C. C. Cheung; Wenjie Che; Qiang Zhou 001; Jinian Bian (FPL, 2013)

RALP: Reconvergence-aware layer partitioning for 3D FPGAs. - Qingyu Liu; Yuchun Ma; Yu Wang 002; Wayne Luk; Jinian Bian (ReConFig, 2013)

Unification of PR Region floorplanning and Fine-Grained Placement for Dynamic Partially Reconfigurable FPGAs. - Ruining He; Guoqiang Liang; Yuchun Ma; Yu Wang 002; Jinian Bian (J. Circuits Syst. Comput., 2013)

Adaptive Selection and Clustering of Partial Reconfiguration Modules for Modern FPGA Design Flow. - Kang Zhao; Yuchun Ma; Ruining He; Jixing Zhang; Ning Xu 006; Jinian Bian (ACM Trans. Reconfigurable Technol. Syst., 2023)