An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions. - Yuichiro Miyaoka; Jinku Choi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (APCCAS (1), 2002)

VLSI Architecture for a Flexible Motion Estimation with Parameters. - Jinku Choi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC/VLSI Design, 2002)

An Algorithm and a Flexible Architecture for Fast Block-Matching Motion Estimation. - Jinku Choi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

A hardware/software partitioning algorithm for SIMD processor cores. - Koichi Tachikake; Nozomu Togawa; Yuichiro Miyaoka; Jinku Choi; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 2003)

A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions. - Nozomu Togawa; Kyosuke Kasahara; Yuichiro Miyaoka; Jinku Choi; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)