The parallel algorithm implementation of matrix multiplication based on ESCA. - Pan Chen; Kui Dai; Dan Wu 009; Jinli Rao; Xuecheng Zou (APCCAS, 2010)

A High Efficient On-Chip Interconnection Network in SIMD CMPs. - Dan Wu 009; Kui Dai; Xuecheng Zou; Jinli Rao; Pan Chen (ICA3PP (1), 2010)

Implementation and evaluation of parallel FFT on Engineering and Scientific Computation Accelerator (ESCA) architecture. - Dan Wu 009; Xuecheng Zou; Kui Dai; Jinli Rao; Pan Chen; Zhaoxia Zheng (J. Zhejiang Univ. Sci. C, 2011)

A Compact Hardware Implementation of SM3 Hash Function. - Tianyong Ao; Zhangqing He; Jinli Rao; Kui Dai; Xuecheng Zou (TrustCom, 2014)

BFWindow: Speculatively Checking Data Property Consistency against Buffer Overflow Attacks. - Jinli Rao; Zhangqing He; Shu Xu; Kui Dai; Xuecheng Zou (IEICE Trans. Inf. Syst., 2016)

Design Exploration of SHA-3 ASIP for IoT on a 32-bit RISC-V Processor. - Jinli Rao; Tianyong Ao; Shu Xu; Kui Dai; Xuecheng Zou (IEICE Trans. Inf. Syst., 2018)

ARCE: Towards Code Pointer Integrity on Embedded Processors Using Architecture-Assisted Run-Time Metadata Management. - Jinli Rao; Tianyong Ao; Kui Dai; Xuecheng Zou (IEEE Comput. Archit. Lett., 2019)