A novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier. - Chunyu Peng; Youwu Tao; Wenjuan Lu; Zhengping Li; Xinchun Ji; Jinlong Yan; Junning Chen (IEICE Electron. Express, 2015)

Erratum: A novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier [IEICE Electronics Express Vol 12 (2015) No 5 pp 20150102]. - Chunyu Peng; Youwu Tao; Wenjuan Lu; Zhengping Li; Xinchun Ji; Jinlong Yan; Junning Chen (IEICE Electron. Express, 2015)

Modeling and Implementation of Electroactive Smart Air-Conditioning Vent Register for Personalized HVAC Systems. - Jinlong Yan; Qi Zeng; Yuan Liang 001; Lei He 001; Zhengping Li (IEEE Access, 2017)

Adaptive Low-Rank Tensor Approximation for SRAM Yield Analysis using Bootstrap Resampling. - Xiao Shi 001; Jinlong Yan; Hao Yan 002; Jiajia Zhang; Jinxin Wang; Longxing Shi; Lei He 001 (ASICON, 2019)

DCS-PCA based Data Transmission in Smart Grid. - Dengjun Zhu; Jinlong Yan; Haiwei Yuan; Yongjun Ma; Xufeng Hu (ICAIIC, 2019)

Data Fusion Analysis with Optimal Weight in Smart Grid. - Dengjun Zhu; Haiwei Yuan; Jinlong Yan; Yanping Qing; Weijie Yang (ICAIIC, 2019)

An IoT-based intelligent irrigation system with data fusion and a self-powered wide-area network. - Li Gong; Jinlong Yan; Yiqiao Chen; Jinjing An; Lei He 001; Lirong Zheng 001; Zhuo Zou (J. Ind. Inf. Integr., 2022)

METAL: A Memory-Efficient Transformer Architecture for Long-Context Inference on FPGA. - Zicheng He; Shaoqiang Lu; Tiandong Zhao; Jinlong Yan; Chen Wu; Lei He 001 (ASAP, 2025)