Periodic steady-state analysis of coupled ODE-AE-CGE systems for MOS RF autonomous circuit simulation. - Xinyu Wu; Zaiman Chen; Jinmei Lai 001; Qianling Zhang; Omar Wing; Junyan Ren (ASP-DAC, 2003)

A design of high speed double precision floating point adder using macro modules. - Chi Huang; Xinyu Wu; Jinmei Lai 001; Chengshou Sun; Gang Li (ASP-DAC, 2005)

Design of A 2.4-GHz integrated frequency synthesizer. - Fei Wang; Jianyu Zhang; Xuan Wang; Jinmei Lai 001; Chengshou Sun (ASP-DAC, 2005)

A novel dynamic reconfigurable VLSI architecture for H.264 transforms. - Wei Cao 002; Hui Hou; Jinmei Lai 001; Jiarong Tong; Hao Min (APCCAS, 2008)

Design and implementation of the configuration circuit for FDP FPGA. - Yabin Wang; Jing Xie; Jinmei Lai 001; Jiarong Tong (APCCAS, 2008)

A high-performance reconfigurable 2-D transform architecture for H.264. - Wei Cao 002; Hui Hou; Jinmei Lai 001; Jiarong Tong; Hao Min (ICECS, 2008)

High-speed and memory-efficient architecture for 2-D 1-Level discrete wavelet transform. - Hui Hou; Wei Cao 002; Fan-jiong Zhang; Jinmei Lai 001; Jiarong Tong (ICECS, 2008)

A high-performance reconfigurable VLSI architecture for vbsme in H.264. - Wei Cao 002; Hui Hou; Jiarong Tong; Jinmei Lai 001; Hao Min (IEEE Trans. Consumer Electron., 2008)

A Flexible Bit-Stream Level Evolvable Hardware Platform Based on FPGA. - HuaQiu Yang; Liguang Chen; ShaoTeng Liu; HaiXiang Bu; Yuan Wang; Jinmei Lai 001 (AHS, 2009)

A delay-optimized universal FPGA routing architecture. - Fang Wu; Huowen Zhang; Lei Duan; Jinmei Lai 001; Yuan Wang; Jiarong Tong (ASP-DAC, 2009)

A novel minloop SB design to improve FPGA routability. - JIanDe Yu; Jinmei Lai 001 (FPGA, 2009)

Research on design method of scalable Configurable IP Core. - Lei Li; Jian Wang 036; Yuan Wang; Jinmei Lai 001 (AHS, 2011)

A new configurable logic block with 4/5-input configurable LUT and fast/slow-path carry chain. - Zhidong Mao; Liguang Chen; Yuan Wang; Jinmei Lai 001 (ASICON, 2011)

FPGA interconnect timing library based on the statistical method. - Xiangzhi Meng; Liguang Chen; Hao Zhou 008; Jian Wang 036; Meng Yang 013; Jinmei Lai 001 (ASICON, 2011)

The design and verification of SEU-hardened configurable DFF. - Xinrui Zhang; Liguang Chen; Liyun Wang; Jian Wang 036; Jinmei Lai 001 (ASICON, 2011)

A novel full coverage test method for CLBs in FPGA (abstract only). - Yong Fu; Chi Wang; Liguang Chen; Jinmei Lai 001 (FPGA, 2012)

A novel memristor-based rSRAM structure for multiple-bit upsets immunity. - Liyun Wang; Chun Zhang; Liguang Chen; Jinmei Lai 001; Jiarong Tong (IEICE Electron. Express, 2012)

A high-resolution TDC implemented in a 90nm process FPGA. - Jinmei Lai 001; Yanquan Luo; Qi Shao; Lichun Bao; Xueling Liu (ASICON, 2013)

Weight-based FPGA placement algorithm with wire effect considered. - Huagang Li; Jian Wang 036; Jinmei Lai 001 (ASICON, 2013)

Improved unified interconnect unit for high speed and scalable FPGA. - Lei Li; Jian Wang 036; Jinmei Lai 001 (ASICON, 2013)

The timing control design of 65nm block RAM in FPGA. - Xinrui Zhang; Jian Wang 036; Dan Chen; Jinmei Lai 001; Lichun Bao; Xueling Liu (ASICON, 2013)

FPGA bitstream compression and decompression using LZ and golomb coding (abstract only). - Jinsong Mao; Hao Zhou 008; Haijiang Ye; Jinmei Lai 001 (FPGA, 2013)

A novel multithread routing method for FPGAs (abstract only). - Chun Zhu; Qiuli Li; Jian Wang 036; Jinmei Lai 001 (FPGA, 2013)

Yet Another Many-Objective Clustering (YAMO-Pack) for FPGA CAD. - Meng Yang 013; Jinmei Lai 001; Jiarong Tong (FPL, 2013)

A novel net-partition-based multithread FPGA routing method. - Chun Zhu; Jian Wang 036; Jinmei Lai 001 (FPL, 2013)

A hierarchical parallel evolvable hardware based on network on chip. - Jun Rong Wang; Dan Wang; Jin-Mei Lai 001 (ReConFig, 2013)

Optimisation of Fixed Polarity Canonical Or-Coincidence Expansions. - Meng Yang 013; Jiarong Tong; Jinmei Lai 001 (J. Comput., 2013)

Optimisation of Mixed Polarity Reed-Muller Functions. - Meng Yang 013; Jinmei Lai 001 (J. Softw., 2013)

Novel FPGA clock network with low latency and skew (abstract only). - Lei Li; Jian Wang 036; Jinmei Lai 001 (FPGA, 2014)

An Architecture Independent Packing Method for LUT-based Commercial FPGA. - Meng Yang 013; Jinmei Lai 001; A. E. A. Almaini (J. Comput., 2014)

FPGA bitstream compression and decompression based on LZ77 algorithm and BMC technique. - Yuanpei Gao; Haijiang Ye; Jian Wang 036; Jinmei Lai 001 (ASICON, 2015)

Iterative optimization algorithm for sound localization. - Fang Sun; Jin-Mei Lai 001 (ASICON, 2015)

A power efficient current-mode differential driver for FPGAs. - Yuanlong Xiao; Jian Wang 036; Jinmei Lai 001 (ASICON, 2015)

A new automatic method for testing interconnect resources in FPGAs based on general routing matrix. - Zhen Yang; Chuanzeng Liang; Jian Wang 036; Jinmei Lai 001 (IEICE Electron. Express, 2015)

Testing FPGA Local Interconnects Based on Repeatable Configuration Modules (Abstract Only). - Zhen Yang; Jian Wang 036; Meng Yang 013; Jinmei Lai 001 (FPGA, 2016)

A universal automatic on-chip measurement of FPGA's internal setup and hold times. - Yuanlong Xiao; Jian Wang 036; Jinmei Lai 001 (IEICE Electron. Express, 2016)

Prototyping design of a flexible DSP block with pipeline structure for FPGA. - Hanyang Xu; Jian Wang 036; Jinmei Lai 001 (IEICE Electron. Express, 2016)

Remote embedded simulation system for SW/HW co-design based on dynamic partial reconfiguration. - Jiaqi Gu; Ruoyao Wang; Jian Wang 036; Jinmei Lai 001; Qinghua Duan (ASICON, 2017)

A deep research on the chip verification platform based on network. - Chuanliang Kang; Pei Yang; Jian Wang 036; Jinmei Lai 001 (ASICON, 2017)

FPGA-based convolution neural network for traffic sign recognition. - Yuchen Yao; Zhiqian Zhang; Zhen Yang; Jian Wang 036; Jinmei Lai 001 (ASICON, 2017)

A SA-based parallel method for FPGA placement. - Chengyu Hu; Peng Lu; Meng Yang 013; Jian Wang 036; Jinmei Lai 001 (IEICE Electron. Express, 2018)

Design of a power efficient self-adaptive LVDS driver. - Hanyang Xu; Jian Wang 036; Jinmei Lai 001 (IEICE Electron. Express, 2018)

A Polymorphic Circuit Interoperability Framework. - Timothy Dunlap; Gang Qu 001; Jinmei Lai 001 (ASICON, 2019)

A Web-based Waveform Viewer for BR0101 Chip Testing Platform. - Xinyu He; Xie Xie; Jinmei Lai 001; Jian Wang 036 (ASICON, 2019)

Balance of memory footprint and runtime for high-density routing in large-scale FPGAs. - Wei Liu; Weilin Cong; Chengyu Hu; Peng Lu; Jinmei Lai 001 (ASICON, 2019)

An Exponential Dynamic Weighted Fair Queuing Algorithm for Task Scheduling in Chip Verification Platform. - Jiafeng Liu; Zhiyin Lu; Xie Xie; Jian Wang 036; Jinmei Lai 001 (ASICON, 2019)

A Low-delay Configurable Register for FPGA. - Zhi-Yin Lu; Jia-Feng Liu; Yunbing Pang; Zhengjie Li; Yufan Zhang; Jin-Mei Lai 001; Jian Wang 036 (ASICON, 2019)

An FPGA-based log-structure Flash memory system for space exploration. - Huanlin Luo; Yunbo Liu; Hai Ren; Tiantian Zhang; Jian Wang 036; Jinmei Lai 001 (ASICON, 2019)

Research on Area Modeling Methodology for FPGA Interconnect Circuits. - Yunbing Pang; Jiqing Xu; Zhiyin Lu; Zhengjie Li; Yufan Zhang; Jinmei Lai 001 (ASICON, 2019)

Design and implementation of Serial ATA pbysical layer on FPGA. - Xie Xie; Qinghua Duan; Jiafeng Liu; Jian Wang 036; Jinmei Lai 001 (ASICON, 2019)

Transistor-Level Optimization Methodology for GRM FPGA Interconnect Circuits. - Zhengjie Li; Yuanlong Xiao; Yufan Zhang; Yunbing Pang; Jian Wang 036; Jinmei Lai 001 (FPGA, 2019)

An Analytical-based Hybrid Algorithm for FPGA Placement. - Chengyu Hu; Qinghua Duan; Liran Hu; Peng Lu; Zhengjie Li; Meng Yang 013; Jian Wang 036; Jinmei Lai 001 (ACM Great Lakes Symposium on VLSI, 2019)

An Automatic Transistor-Level Tool for GRM FPGA Interconnect Circuits Optimization. - Zhengjie Li; Yuanlong Xiao; Yufan Zhang; Yunbing Pang; Chengyu Hu; Jian Wang 036; Jinmei Lai 001 (ACM Great Lakes Symposium on VLSI, 2019)

HRAE: Hardware-assisted Randomization against Adversarial Example Attacks. - Jiliang Zhang 002; Shuang Peng 010; Yupeng Hu; Fei Peng; Wei Hu 008; Jinmei Lai 001; Jing Ye 001; Xiangqi Wang (ATS, 2020)

INTB: A New FPGA Interconnect Model for Architecture Exploration. - Chengyu Hu; Qinghua Duan; Peng Lu; Wei Liu; Jian Wang 036; Jinmei Lai 001 (FPGA, 2020)

FPTLOPT: An Automatic Transistor-Level Optimization Tool for GRM FPGA. - Yufan Zhang; Zhengjie Li; Jian Wang 036; Jinmei Lai 001 (FPGA, 2020)

A Tile-based Interconnect Model for FPGA Architecture Exploration. - Chengyu Hu; Qinghua Duan; Peng Lu; Wei Liu; Jian Wang 036; Jinmei Lai 001 (ACM Great Lakes Symposium on VLSI, 2020)

FABLE-DTS: Hardware-Software Co-Design of a Fast and Stable Data Transmission System for FPGAs. - Jia-Bao Gao; Jian Wang 036; Md Tanvir Arafin; Jin-Mei Lai 001 (SoCC, 2020)

AutoTEA: Automated Transistor-level Efficient and Accurate Optimization for GRM FPGA Design. - Yanze Li; Yufan Zhang; Jiafeng Liu; Jian Wang 036; Jinmei Lai 001; Gang Qu 001 (FCCM, 2021)

TCP-Net: Minimizing Operation Counts of Binarized Neural Network Inference. - Qingliang Liu 002; Jiabao Gao; Jinmei Lai 001 (ISCAS, 2021)

FCA-BNN: Flexible and Configurable Accelerator for Binarized Neural Networks on FPGA. - Jiabao Gao; Yuchen Yao; Zhengjie Li; Jinmei Lai 001 (IEICE Trans. Inf. Syst., 2021)

HBDCA: A Toolchain for High-Accuracy BRAM-Defined CNN Accelerator on FPGA with Flexible Structure. - Zhengjie Li; Jiabao Gao; Jinmei Lai 001 (IEICE Trans. Inf. Syst., 2021)

An Effective Test Method for Block RAMs in Heterogeneous FPGAs Based on a Novel Partial Bitstream Relocation Technique. - Wei Xiong; Yanze Li; Changpeng Sun; Huanlin Luo; Jiafeng Liu; Jian Wang 036; Jinmei Lai 001; Gang Qu 001 (ACM Great Lakes Symposium on VLSI, 2022)

AutoTEA: An Automated Transistor-level Efficient and Accurate design tool for FPGA design. - Yanze Li; Yufan Zhang; Jiafeng Liu; Jun Gong; Jian Wang 036; Jinmei Lai 001; Xinxuan Tao; Gang Qu 001 (Integr., 2022)

3-D Auxiliary Classifier GAN for Hyperspectral Anomaly Detection via Weakly Supervised Learning. - Huanlin Luo; Haowen Zhu; Shengyang Liu; Yichuan Liu; Xinzhong Zhu; Jinmei Lai 001 (IEEE Geosci. Remote. Sens. Lett., 2022)

An Efficient Channel-Aware Sparse Binarized Neural Networks Inference Accelerator. - Qingliang Liu 002; Jinmei Lai 001; Jiabao Gao (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A High-Performance YOLOV5 Accelerator for Object Detection with Near Sensor Intelligence. - Jiacheng Cao; Ziyi Yang; Jie Lu; Jinmei Lai 001 (ASICON, 2023)

An Accurate Area Model for FPGA Circuits at Advanced Technologies. - Yanze Li; Zeyu Sun; Jianfan Zhang; Zhichao Wei; Jian Wang 036; Jinmei Lai 001 (ASICON, 2023)

Optimizing Wirelength And Delay of FPGA Tile through Floorplanning Based on Simulated Annealing Algorithm. - Honghong Long; Yu Bai; Yanze Li; Jian Wang 036; Jinmei Lai 001 (ASICON, 2023)

EdgeMedNet: Lightweight and Accurate U-Net for Implementing Efficient Medical Image Segmentation on Edge Devices. - Qingliang Liu 002; Shuai Zhou; Jinmei Lai 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Testing Method for Embedded UltraRAM in Field Programmable Gate Arrays. - Jiaqi Guo; Wei Xiong; Jian Wang 036; Jinmei Lai 001 (ATS, 2024)

An optimized EEGNet processor for low-power and real-time EEG classification in wearable brain-computer interfaces. - Jiacheng Cao; Wei Xiong; Jie Lu; Peilin Chen; Jian Wang 036; Jinmei Lai 001; Miaoqing Huang (Microelectron. J., 2024)

A Reliable and Efficient Online Solution for Adaptive Voltage and Frequency Scaling on FPGAs. - Wei Xiong; Jiacheng Cao; Yaozhang Liu; Jian Wang 036; Jinmei Lai 001; Miaoqing Huang (IEEE Trans. Very Large Scale Integr. Syst., 2024)

An Efficient Traversal Method for FPGA Interconnect Testing Based on Regular Routing. - Wenwei Chen; Lin Ye; XiaoTong Zhao; Tongshu Ding; Jian Wang 036; Jinmei Lai 001 (FPGA, 2025)

Shrink eFPGA tile area by using custom cells and optimizing routing congestion. - Yanze Li; Jian Wang 036; Jinmei Lai 001 (Microelectron. J., 2025)