CMOS nonthreshold logic (NTL) and cascode nonthreshold logic (CNTL) for high-speed applications. - Jinn-Shyan Wang; Chung-Yu Wu; Ming-Kai Tsai (IEEE J. Solid State Circuits, 1989)

Analysis and design of a new race-free four-phase CMOS logic. - Chung-Yu Wu; Kuo-Hsing Cheng; Jinn-Shyan Wang (IEEE J. Solid State Circuits, 1993)

Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits. - Hong-Yi Huang; Jinn-Shyan Wang; Yuan-Hua Chu; Tain-Shun Wu; Kuo-Hsing Cheng; Chung-Yu Wu (ISCAS, 1995)

Low-power embedded SRAM macros with current-mode read/write operations. - Jinn-Shyan Wang; Po-Hui Yang; Wayne Tseng (ISLPED, 1998)

Technnology Mapping for Low Power. - Ching-Wei Yeh; Chin-Chao Chang; Jinn-Shyan Wang (ASP-DAC, 1999)

Layout Techniques Supporting the Use of Dual Supply Voltages for Cell-based Designs. - Ching-Wei Yeh; Yin-Shuin Kang; Shan-Jih Shieh; Jinn-Shyan Wang (DAC, 1999)

Charge Sharing Fault Detection for CMOS Domino Logic Circuits. - Ching-Hwa Cheng; Shih-Chieh Chang; Jinn-Shyan Wang; Wen-Ben Jone (DFT, 1999)

A new high-speed/low-power dynamic CMOS logic and its application to the design of an AOI-type ROM. - Ching-Rong Chang; Jinn-Shyan Wang (ISCAS (1), 1999)

A cell selection strategy for low power applications. - Chingwei Yeh; Chin-Chao Chang; Jinn-Shyan Wang (ISCAS (6), 1999)

Segmented bus design for low-power systems. - J.-Y. Chen; Wen-Ben Jone; Jinn-Shyan Wang; Hsueh-I Lu; Tien-Fu Chen (IEEE Trans. Very Large Scale Integr. Syst., 1999)

A new CMAC neural network architecture and its ASIC realization. - Yuan-Bao Hsu; Kao-Shing Hwang; Chien-Yuan Pao; Jinn-Shyan Wang (ASP-DAC, 2000)

Power analysis and implementation of a low-power 300 MHz 8-b × 8-b pipelined multiplier. - Jinn-Shyan Wang; Po-Hui Yang (ASP-DAC, 2000)

Charge sharing fault analysis and testing for CMOS domino logic circuits. - Ching-Hwa Cheng; Wen-Ben Jone; Jinn-Shyan Wang; Shih-Chieh Chang (Asian Test Symposium, 2000)

Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits. - Ching-Hwa Cheng; Jinn-Shyan Wang; Shih-Chieh Chang; Wen-Ben Jone (DFT, 2000)

Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation. - Ching-Hwa Cheng; Shih-Chieh Chang; Shin-De Li; Wen-Ben Jone; Jinn-Shyan Wang (ICCAD, 2000)

A high-speed single-phase-clocked CMOS priority encoder. - Jinn-Shyan Wang; Chun-Shing Huang (ISCAS, 2000)

A compact adaptive equalizer IC for HIPERLAN system. - Jinn-Shyan Wang; Pei-Lung Lin; Wern-Ho Sheen; Duo Sheng; Yu-Ming Huang (ISCAS, 2000)

A 1-GHz low-power transposition memory using new pulse-clocked D flip-flops. - Po-Hui Yang; Jinn-Shyan Wang; Yi-Ming Wang (ISCAS, 2000)

High-speed and low-power CMOS priority encoders. - Jinn-Shyan Wang; Chung-Hsun Huang (IEEE J. Solid State Circuits, 2000)

Low-power embedded SRAM with the current-mode write technique. - Jinn-Shyan Wang; Wayne Tseng; Hung-Yu Li (IEEE J. Solid State Circuits, 2000)

Design of a 3-V 300-MHz low-power 8-b×8-b pipelined multiplier using pulse-triggered TSPC flip-flops. - Jinn-Shyan Wang; Po-Hui Yang; Duo Sheng (IEEE J. Solid State Circuits, 2000)

Design of low-power domino circuits using multiple supply voltages. - Shang-Jyh Shieh; Jinn-Shyan Wang (ICECS, 2001)

A contention-alleviated static keeper for high-performance domino logic circuits. - Shang-Jyh Shieh; Jinn-Shyan Wang; Yuan-Hsun Yeh (ICECS, 2001)

A high-speed CMOS incrementer/decrementer. - Chung-Hsun Huang; Jinn-Shyan Wang; Yan-Chao Huang (ISCAS (4), 2001)

A high-efficiency CMOS charge pump circuit. - Sheng-Yeh Lai; Jinn-Shyan Wang (ISCAS (4), 2001)

Low-power and high-speed ROM modules for ASIC applications. - Ching-Rong Chang; Jinn-Shyan Wang; Cheng-Hui Yang (IEEE J. Solid State Circuits, 2001)

Analysis and design of high-speed and low-power CMOS PLAs. - Jinn-Shyan Wang; Ching-Rong Chang; Chingwei Yeh (IEEE J. Solid State Circuits, 2001)

Charge-sharing alleviation and detection for CMOS domino circuits. - Shih-Chieh Chang; Ching-Hwa Cheng; Wen-Ben Jone; Shin-De Lee; Jinn-Shyan Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

An Associative Architecture of CMAC for Mobile Robot Motion Control. - Yuan-Pao Hsu; Kao-Shing Hwang; Jinn-Shyan Wang (J. Inf. Sci. Eng., 2002)

Design of high-performance CMOS priority encoders and incrementer/decrementers using multilevel lookahead and multilevel folding techniques. - Chung-Hsun Huang; Jinn-Shyan Wang; Yan-Chao Huang (IEEE J. Solid State Circuits, 2002)

Low-voltage pulsewidth control loops for SOC applications. - Po-Hui Yang; Jinn-Shyan Wang (IEEE J. Solid State Circuits, 2002)

Energy Efficient Caching-on-Cache Architectures for Embedded Systems. - Hung-Cheng Wu; Tien-Fu Chen; Hung-Yu Li; Jinn-Shyan Wang (J. Inf. Sci. Eng., 2003)

High-performance and power-efficient CMOS comparators. - Chung-Hsun Huang; Jinn-Shyan Wang (IEEE J. Solid State Circuits, 2003)

Design theory and implementation for low-power segmented bus systems. - Wen-Ben Jone; Jinn-Shyan Wang; Hsueh-I Lu; I. P. Hsu; J.-Y. Chen (ACM Trans. Design Autom. Electr. Syst., 2003)

A reliable low-power fast skew-compensation circuit. - Yi-Ming Wang; Jinn-Shyan Wang (ASP-DAC, 2004)

A power-aware SNR-progressive DCT/IDCT IP core design for multimedia transform coding. - Kuan-Hung Chen; Jiun-In Guo; Jinn-Shyan Wang; Ching-Wei Yeh (ICME, 2004)

A power-aware IP core design for the variable-length DCT/IDCT targeting at MPEG4 shape-adaptive transforms. - Kuan-Hung Chen; Jiun-In Guo; Jinn-Shyan Wang; Ching-Wei Yeh; Tien-Fu Chen (ISCAS (2), 2004)

Pseudo-footless CMOS domino logic circuits for high-performance VLSI designs. - Jinn-Shyan Wang; Shang-Jyh Shieh; Ching-Wei Yeh; Yuan-Hsun Yeh (ISCAS (2), 2004)

An all-digital 50% duty-cycle corrector. - Yi-Ming Wang; Jinn-Shyan Wang (ISCAS (2), 2004)

Low-power fixed-width array multipliers. - Jinn-Shyan Wang; Chien-Nan Kuo; Tsung-Han Yang (ISLPED, 2004)

The CMOS carry-forward adders. - Chung-Hsun Huang; Jinn-Shyan Wang; Chingwei Yeh; Chih-Jen Fang (IEEE J. Solid State Circuits, 2004)

A low-power half-delay-line fast skew-compensation circuit. - Yi-Ming Wang; Jinn-Shyan Wang (IEEE J. Solid State Circuits, 2004)

An efficient direct 2-D transform coding IP design for MPEG-4 AVC/H.264. - Kuan-Hung Chen; Jiun-In Guo; Jinn-Shyan Wang (ISCAS (5), 2005)

An all-digital pulsewidth control loop. - Yi-Ming Wang; Chang-Fen Hu; Yi-Jen Chen; Jinn-Shyan Wang (ISCAS (2), 2005)

A low-power high-SFDR CMOS direct digital frequency synthesizer. - Jinn-Shyan Wang; Shiang-Jiun Lin; Chingwei Yeh (ISCAS (2), 2005)

An efficient spurious power suppression technique (SPST) and its applications on MPEG-4 AVC/H.264 transform coding design. - Kuan-Hung Chen; Kuo-Chuan Chao; Jinn-Shyan Wang; Yuan-Sun Chu; Jiun-In Guo (ISLPED, 2005)

Design techniques for single-low-VDD CMOS systems. - Jinn-Shyan Wang; Hung-Yu Li; Chingwei Yeh; Tien-Fu Chen (IEEE J. Solid State Circuits, 2005)

An Energy-Aware IP Core Design for the Variable-Length DCT/IDCT Targeting at MPEG4 Shape-Adaptive Transforms. - Kuan-Hung Chen; Jiun-In Guo; Jinn-Shyan Wang; Ching-Wei Yeh; Jia-Wei Chen (IEEE Trans. Circuits Syst. Video Technol., 2005)

An 830mW, 586kbps 1024-bit RSA chip design. - Chingwei Yeh; En-Feng Hsu; Kai-Wen Cheng; Jinn-Shyan Wang; Nai-Jen Chang (DATE Designers' Forum, 2006)

A 124.8Msps, 15.6mW field-programmable variable-length codec for multimedia applications. - Chingwei Yeh; Chao-Ching Wang; Lin-Chi Lee; Jinn-Shyan Wang (DATE Designers' Forum, 2006)

Low Complexity Architecture Design of H.264 Predictive Pixel Compensator for HDTV Application. - Jia-Wei Chen; Chien-Chang Lin; Jiun-In Guo; Jinn-Shyan Wang (ICASSP (3), 2006)

A Condition-based Intra Prediction Algorithm for H.264/AVC. - Jia-Wei Chen; Chun-Hao Chang; Chien-Chang Lin; Yi-Huan Yang; Jiun-In Guo; Jinn-Shyan Wang (ICME, 2006)

A performance-aware IP core design for multimode transform coding using scalable-DA algorithm. - Jia-Wei Chen; Kuan-Hung Chen; Jinn-Shyan Wang; Jiun-In Guo (ISCAS, 2006)

Design of STR level converters for SoCs using the multi-island dual-VDD design technique. - Jinn-Shyan Wang; Yu-Juey Chang; Chingwei Yeh; Yuan-Hua Chu (ISCAS, 2006)

An improved SAR controller for DLL applications. - Jinn-Shyan Wang; Yi-Ming Wang; Chun-Yuan Cheng; Yu-Chia Liu (ISCAS, 2006)

TCAM for IP-Address Lookup Using Tree-style AND-type Match Lines and Segmented Search Lines. - Jinn-Shyan Wang; Chao-Ching Wang; Chingwei Yeh (ISSCC, 2006)

An AND-type match-line scheme for high-performance energy-efficient content addressable memories. - Hung-Yu Li; Chia-Cheng Chen; Jinn-Shyan Wang; Chingwei Yeh (IEEE J. Solid State Circuits, 2006)

A high-performance direct 2-D transform coding IP design for MPEG-4AVC/H.264. - Kuan-Hung Chen; Jiun-In Guo; Jinn-Shyan Wang (IEEE Trans. Circuits Syst. Video Technol., 2006)

A 7mW-to-183mW Dynamic Quality-Scalable H.264 Video Encoder Chip. - Hsiu-Cheng Chang; Jia-Wei Chen; Ching-Lung Su; Yao-Chang Yang; Yao Li; Chun-Hao Chang; Ze-Min Chen; Wei-Sen Yang; Chien-Chang Lin; Ching-Wen Chen; Jinn-Shyan Wang; Jiun-In Guo (ISSCC, 2007)

A 230mV-to-500mV 375KHz-to-16MHz 32b RISC Core in 0.18μm CMOS. - Jinn-Shyan Wang; Jian-Shiun Chen; Yi-Ming Wang; Chingwei Yeh (ISSCC, 2007)

A Quality Scalable H.264/AVC Baseline Intra Encoder for High Definition Video Applicaitons. - Chun-Hao Chang; Jia-Wei Chen; Hsiu-Cheng Chang; Yao-Chang Yang; Jinn-Shyan Wang; Jiun-In Guo (SiPS, 2007)

A 160K Gates/4.5 KB SRAM H.264 Video Decoder for HDTV Applications. - Chien-Chang Lin; Jia-Wei Chen; Hsiu-Cheng Chang; Yao-Chang Yang; Yi-Huan Ou-Yang; Ming-Chih Tsai; Jiun-In Guo; Jinn-Shyan Wang (IEEE J. Solid State Circuits, 2007)

A low-voltage latch-adder based tree multiplier. - Tzu-Yuan Kuo; Jinn-Shyan Wang (ISCAS, 2008)

High-Speed and Low-Power Design Techniques for TCAM Macros. - Chao-Ching Wang; Jinn-Shyan Wang; Chingwei Yeh (IEEE J. Solid State Circuits, 2008)

A dynamic quality-scalable H.264 video encoder chip. - Hsiu-Cheng Chang; Yao-Chang Yang; Jia-Wei Chen; Ching-Lung Su; Cheng-An Chien; Jiun-In Guo; Jinn-Shyan Wang (ASP-DAC, 2009)

No cache-coherence: a single-cycle ring interconnection for multi-core L1-NUCA sharing on 3D chips. - Shu-Hsuan Chou; Chien-Chih Chen; Chi-Neng Wen; Yi-Chao Chan; Tien-Fu Chen; Chao-Ching Wang; Jinn-Shyan Wang (DAC, 2009)

A Dynamic Quality-scalable H.264 Video Encoder. - Hsiu-Cheng Chang; Jia-Wei Chen; Yao-Chang Yang; Cheng-An Chien; Tzu-Chun Chang; Jinn-Shyan Wang; Jiun-In Guo (ISCAS, 2009)

An Adaptively Dividable Dual-Port BiTCAM for Virus-Detection Processors in Mobile Devices. - Chao-Ching Wang; Chieh-Jen Cheng; Tien-Fu Chen; Jinn-Shyan Wang (IEEE J. Solid State Circuits, 2009)

A Dynamic Quality-Adjustable H.264 Video Encoder for Power-Aware Video Applications. - Hsiu-Cheng Chang; Jia-Wei Chen; Bing-Tsung Wu; Ching-Lung Su; Jinn-Shyan Wang; Jiun-In Guo (IEEE Trans. Circuits Syst. Video Technol., 2009)

VisoMT: A Collaborative Multithreading Multicore Processor for Multimedia Applications With a Fast Data Switching Mechanism. - Wei-Chun Ku; Shu-Hsuan Chou; Jui-Chin Chu; Chi-Lin Liu; Tien-Fu Chen; Jiun-In Guo; Jinn-Shyan Wang (IEEE Trans. Circuits Syst. Video Technol., 2009)

A 55nm 1GHz one-cycle-locking de-skewing circuit. - Jinn-Shyan Wang; Chun-Yuan Cheng; Je-Ching Liu; Yu-Chia Liu; Yi-Ming Wang (ISCAS, 2010)

Heuristic Sizing Methodology for Designing High-Performance CMOS Level Converters with Balanced Rise and Fall Delays. - Jinn-Shyan Wang; Yu-Juey Chang; Chingwei Yeh (IEICE Trans. Electron., 2010)

A Duty-Cycle-Distortion-Tolerant Half-Delay-Line Low-Power Fast-Lock-in All-Digital Delay-Locked Loop. - Jinn-Shyan Wang; Chun-Yuan Cheng; Je-Ching Liu; Yu-Chia Liu; Yi-Ming Wang (IEEE J. Solid State Circuits, 2010)

ADDLL/VDD-biasing co-design for process characterization, performance calibration, and clock synchronization in variation-tolerant designs. - Jinn-Shyan Wang; Yung-Chen Chien; Jia-Hong Lin; Chun-Yuan Cheng; Ying-Ting Ma; Chung-Hsun Huang (ASICON, 2011)

Low power shift registers for megabits CMOS image sensors. - Jinn-Shyan Wang; Tsung-Han Hsieh; Keng-Jui Chang; Chingwei Yeh (ASICON, 2011)

Variation-resilient voltage generation for SRAM weak cell testing. - Chingwei Yeh; Yan-Nan Liu; Jinn-Shyan Wang; Pei-Yao Chang (ASICON, 2011)

A H.264/MPEG-2 dual mode video decoder chip supporting temporal/spatial scalable video. - Cheng-An Chien; Yao-Chang Yang; Hsiu-Cheng Chang; Jia-Wei Chen; Cheng-Yen Chang; Jiun-In Guo; Jinn-Shyan Wang; Ching-Hwa Cheng (ASP-DAC, 2011)

RSCE-aware ultra-low-voltage 40-nm CMOS circuits. - Jinn-Shyan Wang; Keng-Jui Chang; Shu-Yi Yang; Tsung-Han Hsieh; Chingwei Yeh (ISOCC, 2011)

Design of Subthreshold SRAMs for Energy-Efficient Quality-Scalable Video Applications. - Jinn-Shyan Wang; Pei-Yao Chang; Tai-Shin Tang; Jia-Wei Chen; Jiun-In Guo (IEEE J. Emerg. Sel. Topics Circuits Syst., 2011)

Design of High-Performance CMOS Level Converters Considering PVT Variations. - Jinn-Shyan Wang; Yu-Juey Chang; Chingwei Yeh (IEICE Trans. Electron., 2011)

A dynamic quality-adjustable H.264 intra coder. - Jia-Wei Chen; Hsiu-Cheng Chang; Jinn-Shyan Wang; Jiun-In Guo (IEEE Trans. Consumer Electron., 2011)

Design of a 2.5-GHz, 3-ps jitter, 8-locking-cycle, all-digital delay-locked loop with cycle-by-cycle phase adjustment. - Chun-Yuan Cheng; Jinn-Shyan Wang; Cheng-Tai Yeh; Jenn-Shyan Sheu (VLSIC, 2012)

Design of 65 nm Sub-Threshold SRAM Using the Bitline Leakage Prediction Scheme and the Non-trimmed Sense Amplifier. - Jinn-Shyan Wang; Pei-Yao Chang; Chi-Chang Lin (IEICE Trans. Electron., 2012)

An ultra Low-voltage/Power-Efficient All-Digital Delay Locked Loop in 55 nm CMOS Technology. - Chun-Yuan Cheng; Jinn-Shyan Wang; Cheng-Tai Yeh (J. Circuits Syst. Comput., 2012)

A 4R/2W Register File Design for UDVS Microprocessors in 65-nm CMOS. - Pei-Yao Chang; Tay-Jyi Lin; Jinn-Shyan Wang; Yen-Hsiang Yu (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

A Scalable High-Performance Virus Detection Processor Against a Large Pattern Set for Embedded Network Security. - Chieh-Jen Cheng; Chao-Ching Wang; Wei-Chun Ku; Tien-Fu Chen; Jinn-Shyan Wang (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Towards Process Variation-Aware Power Gating. - Chingwei Yeh; Yuan-Chang Chen; Jinn-Shyan Wang (IEEE Trans. Very Large Scale Integr. Syst., 2012)

An energy-efficient truly all-digital temperature sensor for SoC applications. - Tzu-Yuan Kuo; Keng-Jui Chang; Jen-Hsiang Lee; Zong-Wu He; Jinn-Shyan Wang (ACM Great Lakes Symposium on VLSI, 2013)

Self-super-cutoff power gating with state retention on a 0.3V 0.29fJ/cycle/gate 32b RISC core in 0.13µm CMOS. - Jian-Shiun Chen; Chingwei Yeh; Jinn-Shyan Wang (ISSCC, 2013)

A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS. - Tay-Jyi Lin; Cheng-An Chien; Pei-Yao Chang; Ching-Wen Chen; Po-Hao Wang; Ting-Yu Shyu; Chien-Yung Chou; Shien-Chun Luo; Jiun-In Guo; Tien-Fu Chen; Gene C. H. Chuang; Yuan-Hua Chu; et al. (ISSCC, 2013)

Variation-aware and adaptive-latency accesses for reliable low voltage caches. - Po-Hao Wang; Wei-Chung Cheng; Yung-Hui Yu; Tang-Chieh Kao; Chi-Lun Tsai; Pei-Yao Chang; Tay-Jyi Lin; Jinn-Shyan Wang; Tien-Fu Chen (VLSI-SoC, 2013)

A high-throughput and high-capacity IPv6 routing lookup system. - Yi-Mao Hsiao; Yuan-Sun Chu; Jeng-Farn Lee; Jinn-Shyan Wang (Comput. Networks, 2013)

Embedding Repeaters in Silicon IPs for Cross-IP Interconnections. - Jinn-Shyan Wang; Keng-Jui Chang; Chingwei Yeh; Shih-Chieh Chang (IEEE Trans. Very Large Scale Integr. Syst., 2013)

A 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW 0.0153-mm2 all-digital delay-locked loop in 65-nm CMOS. - Chun-Yuan Cheng; Jinn-Shyan Wang; Pei-Yuan Chou; Shiou-Ching Chen; Chi-Tien Sun; Yuan-Hua Chu; Tzu-Yi Yang (A-SSCC, 2014)

Low power fixed-latency DSP accelerator with autonomous minimum energy tracking (AMET). - Chung-Hsun Huang; Wei-Jen Chen; Keng-Jui Chang; Yi-Hsuan Ting; Keng-Chang Hsu; Yu-Fu Pan; Chao-Chun Chen; Yuan-Hua Chu; Tay-Jyi Lin; Jinn-Shyan Wang (Hot Chips Symposium, 2014)

Low-cost low-power droop-voltage-aware delay-fault-prevention designs for DVS caches. - Pei-Yuan Chou; I-Chen Wu; Jai-Wei Lin; Xuan-Yu Lin; Tien-Fu Chen; Tay-Jyi Lin; Jinn-Shyan Wang (ASICON, 2015)

A Wide-Range, Low-Power, All-Digital Delay-Locked Loop With Cyclic Half-Delay-Line Architecture. - Jinn-Shyan Wang; Chun-Yuan Cheng; Pei-Yuan Chou; Tzu-Yi Yang (IEEE J. Solid State Circuits, 2015)

An All-Digital Delay-Locked Loop Using an In-Time Phase Maintenance Scheme for Low-Jitter Gigahertz Operations. - Jinn-Shyan Wang; Chun-Yuan Cheng (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A Calibration-Free PVTD-Variation-Tolerant Sensing Scheme for Footless-8T SRAM Designs. - Jinn-Shyan Wang; Yung-Chen Chien; Fengzhi Liu; Pei-Yao Chang (IEEE Trans. Multi Scale Comput. Syst., 2015)

Design of an all-digital temperature sensor in 28 nm CMOS using temperature-sensitive delay cells and adaptive-1P calibration for error reduction. - Shang-Yi Li; Pei-Yuan Chou; Jinn-Shyan Wang (ASP-DAC, 2016)

Variable-length VLIW encoding for code size reduction in embedded processors. - Ting-Yu Shyu; Bo-Yu Su; Tay-Jyi Lin; Chingwei Yeh; Jinn-Shyan Wang; Tien-Fu Chen (SoCC, 2016)

Overoptimistic voltage scaling in pre-error AVS systems and learning-based alleviation. - Yi-Hsuan Ting; Chih-Yang Wang; Yu-Sian Chang; Tay-Jyi Lin; Shih-Chieh Chang; Jinn-Shyan Wang (SoCC, 2016)

Cross-matching caches: Dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors. - Po-Hao Wang; Shang-Jen Tsai; Rizal Tanjung; Tay-Jyi Lin; Jinn-Shyan Wang; Tien-Fu Chen (Integr., 2016)

Zero-Counting and Adaptive-Latency Cache Using a Voltage-Guardband Breakthrough for Energy-Efficient Operations. - Po-Hao Wang; Wei-Chung Cheng; Yung-Hui Yu; Tang-Chieh Kao; Chi-Lun Tsai; Pei-Yao Chang; Tay-Jyi Lin; Jinn-Shyan Wang; Tien-Fu Chen (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

An all-n-type dynamic adder for ultra-low-leakage IoT devices. - Ya-Bei Fang; Pei-Yuan Chou; Bo-Hao Chen; Tay-Jyi Lin; Jinn-Shyan Wang (ASICON, 2017)

Approximate Distributed Arithmetic for Variable-Latency Table Lookup. - Yi-Hsuan Ting; Tay-Jyi Lin; Cheng-Chun Chang; Chih-Chien Hu; Chingwei Yeh; Jinn-Shyan Wang (NGCAS, 2017)

ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures. - Po-Hao Wang; Yung-Chen Chien; Shang-Jen Tsai; Xuan-Yu Lin; Rizal Tanjung; Yi-Sian Lin; Shu-Wei Syu; Tay-Jyi Lin; Jinn-Shyan Wang; Tien-Fu Chen (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Process/Voltage/Temperature-Variation-Aware Design and Comparative Study of Transition-Detector-Based Error-Detecting Latches for Timing-Error-Resilient Pipelined Systems. - Jinn-Shyan Wang; Shih-Nung Wei (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Near-Threshold CORDIC Design with Dynamic Circuitry for Long-Standby IoT Applications. - Pei-Yuan Chou; Ya-Bei Fang; Bo-Hao Chen; Chien-Tung Liu; Tay-Jyi Lin; Jinn-Shyan Wang (SoCC, 2018)

A Low-Area, Low-Power, and Low-Leakage Error-Detecting Latch for Timing-Error Resilient System Designs. - Chien-Tung Liu; Zhe-Wei Chang; Shih-Nung Wei; Jinn-Shyan Wang; Tay-Jyi Lin (SoCC, 2018)

A 0.2 V 32-Kb 10T SRAM With 41 nW Standby Power for IoT Applications. - Yung-Chen Chien; Jinn-Shyan Wang (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

An All-Digital On-Chip Peak-to-Peak Jitter Measurement Circuit With Automatic Resolution Calibration for High PVT-Variation Resilience. - Pei-Yuan Chou; Jinn-Shyan Wang (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A 0.21V 40nm NAND-ROM for IoT Sensing Systems with Long Standby Periods. - Jinn-Shyan Wang; Cheng-Xin Xue; Chien-Tung Liu; Tay-Jyi Lin (ISCAS, 2020)

Low-Active-Energy and Low-Standby-Power Sub-threshold ROM for IoT Edge Sensing Systems. - Jinn-Shyan Wang; Chien-Tung Liu; Chao-Hsiang Wang (VLSI-DAT, 2020)

A 40nm CMOS SoC for Real-Time Dysarthric Voice Conversion of Stroke Patients. - Tay-Jyi Lin; Chen-Zong Liao; You-Jia Hu; Wei-Cheng Hsu; Zheng-Xian Wu; Shao-Yu Wang; Chun-Ming Huang; Ying-Hui Lai; Chingwei Yeh; Jinn-Shyan Wang (ASP-DAC, 2022)

A 16 nm 140 TOPS/W 5 μJ/Inference Keyword Spotting Engine Based on 1D-BCNN. - Tay-Jyi Lin; Yi-Hsuan Ting; Meng-Ze Hsu; Kuan-Han Lin; Chung-Ming Huang; Fu-Cheng Tsai; Shyh-Shyuan Sheu; Shih-Chieh Chang; Chingwei Yeh; Jinn-Shyan Wang (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

In-Situ Critical-Path Replica for Variation-Aware Low-Power Designs with Timing Margin Detection. - Jinn-Shyan Wang; Yong-Chin Miu; Chia-Hua Wu (APCCAS, 2024)

A 40-nm 13.88-TOPS/W FC-DNN Engine for 16-bit Intelligent Audio Processing Featuring Weight-Sharing and Approximate Computing. - Tay-Jyi Lin; Ze Li; Yun-Cheng Chen; Chien-Tung Liu; Tien-Fu Chen; Jinn-Shyan Wang (HCS, 2024)

Design of synthesizable period-jitter sensor IP with high power reduction and variation resiliency. - Jinn-Shyan Wang; Yu-Hsuan Kuo (Integr., 2024)

Clock Period-Jitter Measurement With Low-Noise Runtime Calibration for Chips in FinFET CMOS. - Jinn-Shyan Wang; Pei-Yuan Chou (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A 0.5-V 125-MHz 256-Kb 22-nm SRAM With 10-aJ/bit Active Energy and 10-pW/bit Shutdown Power. - Jinn-Shyan Wang; Chien-Tung Liu; Yu-Chuan Hou (IEEE J. Solid State Circuits, 2025)