Performance-aware task scheduling for energy harvesting nonvolatile processors considering power switching overhead. - Hehe Li; Yongpan Liu; Chenchen Fu; Chun Jason Xue; Donglai Xiang; Jinshan Yue; Jinyang Li 002; Daming Zhang; Jingtong Hu; Huazhong Yang (DAC, 2016)

CNN-based pattern recognition on nonvolatile IoT platform for smart ultraviolet monitoring: (Invited paper). - Jinyang Li 002; Qingwei Guo; Fang Su; Zhe Yuan; Jinshan Yue; Jingtong Hu; Huazhong Yang; Yongpan Liu (ICCAD, 2017)

CORAL: Coarse-grained reconfigurable architecture for Convolutional Neural Networks. - Zhe Yuan; Yongpan Liu; Jinshan Yue; Jinyang Li 002; Huazhong Yang (ISLPED, 2017)

Data Backup Optimization for Nonvolatile SRAM in Energy Harvesting Sensor Nodes. - Yongpan Liu; Jinshan Yue; Hehe Li; Qinghang Zhao; Mengying Zhao; Chun Jason Xue; Guangyu Sun 003; Meng-Fan Chang; Huazhong Yang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Sticker: A 0.41-62.1 TOPS/W 8Bit Neural Network Processor with Multi-Sparsity Compatible Convolution Arrays and Online Tuning Acceleration for Fully Connected Layers. - Zhe Yuan; Jinshan Yue; Huanrui Yang; Zhibo Wang 004; Jinyang Li 002; Yixiong Yang; Qingwei Guo; Xueqing Li 002; Meng-Fan Chang; Huazhong Yang; Yongpan Liu (VLSI Circuits, 2018)

PATH: Performance-Aware Task Scheduling for Energy-Harvesting Nonvolatile Processors. - Jinyang Li 002; Yongpan Liu; Hehe Li; Zhe Yuan; Chenchen Fu; Jinshan Yue; Xiaoyu Feng; Chun Jason Xue; Jingtong Hu; Huazhong Yang (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Accelerating CNN-RNN Based Machine Health Monitoring on FPGA. - Xiaoyu Feng; Jinshan Yue; Qingwei Guo; Huazhong Yang; Yongpan Liu (AICAS, 2019)

AERIS: area/energy-efficient 1T2R ReRAM based processing-in-memory neural network system-on-a-chip. - Jinshan Yue; Yongpan Liu; Fang Su; Shuangchen Li; Zhe Yuan; Zhibo Wang 004; Wenyu Sun; Xueqing Li 002; Huazhong Yang (ASP-DAC, 2019)

A Sparse-Adaptive CNN Processor with Area/Performance balanced N-Way Set-Associate PE Arrays Assisted by a Collision-Aware Scheduler. - Zhe Yuan; Jingyu Wang 004; Yixiong Yang; Jinshan Yue; Zhibo Wang 004; Xiaoyu Feng; Yanzhi Wang 001; Xueqing Li 002; Huazhong Yang; Yongpan Liu (A-SSCC, 2019)

A 65nm 0.39-to-140.3TOPS/W 1-to-12b Unified Neural Network Processor Using Block-Circulant-Enabled Transpose-Domain Acceleration with 8.1 × Higher TOPS/mm2and 6T HBST-TRAM-Based 2D Data-Reuse Architecture. - Jinshan Yue; Ruoyang Liu; Wenyu Sun; Zhe Yuan; Zhibo Wang 004; Yung-Ning Tu; Yi-Ju Chen; Ao Ren; Yanzhi Wang 001; Meng-Fan Chang; Xueqing Li 002; Huazhong Yang; et al. (ISSCC, 2019)

A 3.77TOPS/W Convolutional Neural Network Processor With Priority-Driven Kernel Optimization. - Jinshan Yue; Yongpan Liu; Zhe Yuan; Zhibo Wang 004; Qingwei Guo; Jinyang Li 002; Chengmo Yang; Huazhong Yang (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

High PE Utilization CNN Accelerator with Channel Fusion Supporting Pattern-Compressed Sparse Neural Networks. - Jingyu Wang 004; Songming Yu; Jinshan Yue; Zhe Yuan; Zhuqing Yuan; Huazhong Yang; Xueqing Li 002; Yongpan Liu (DAC, 2020)

RL Based Network Accelerator Compiler for Joint Compression Hyper-Parameter Search. - Xiaoyu Feng; Jinshan Yue; Zhe Yuan; Huazhong Yang; Yongpan Liu (ISCAS, 2020)

14.2 A 65nm 24.7µJ/Frame 12.3mW Activation-Similarity-Aware Convolutional Neural Network Video Processor Using Hybrid Precision, Inter-Frame Data Reuse and Mixed-Bit-Width Difference-Frame Data Codec. - Zhe Yuan; Yixiong Yang; Jinshan Yue; Ruoyang Liu; Xiaoyu Feng; Zhiting Lin; Xiulong Wu; Xueqing Li 002; Huazhong Yang; Yongpan Liu (ISSCC, 2020)

14.3 A 65nm Computing-in-Memory-Based CNN Processor with 2.9-to-35.8TOPS/W System Energy Efficiency Using Dynamic-Sparsity Performance-Scaling Architecture and Energy-Efficient Inter/Intra-Macro Data Reuse. - Jinshan Yue; Zhe Yuan; Xiaoyu Feng; Yifan He 003; Zhixiao Zhang; Xin Si; Ruhui Liu; Meng-Fan Chang; Xueqing Li 002; Huazhong Yang; Yongpan Liu (ISSCC, 2020)

High Area/Energy Efficiency RRAM CNN Accelerator with Kernel-Reordering Weight Mapping Scheme Based on Pattern Pruning. - Songming Yu; Yongpan Liu; Lu Zhang 074; Jingyu Wang 004; Jinshan Yue; Zhuqing Yuan; Xueqing Li 002; Huazhong Yang (CoRR, 2020)

STICKER: An Energy-Efficient Multi-Sparsity Compatible Accelerator for Convolutional Neural Networks in 65-nm CMOS. - Zhe Yuan; Yongpan Liu; Jinshan Yue; Yixiong Yang; Jingyu Wang 004; Xiaoyu Feng; Jian Zhao 004; Xueqing Li 002; Huazhong Yang (IEEE J. Solid State Circuits, 2020)

Block-Circulant Neural Network Accelerator Featuring Fine-Grained Frequency-Domain Quantization and Reconfigurable FFT Modules. - Yifan He 003; Jinshan Yue; Yongpan Liu; Huazhong Yang (ASP-DAC, 2021)

A Non-Volatile Computing-In-Memory Framework With Margin Enhancement Based CSA and Offset Reduction Based ADC. - Yuxuan Huang; Yifan He 003; Jinshan Yue; Huazhong Yang; Yongpan Liu (ASP-DAC, 2021)

A Sort-Less FPGA-Based Non-Maximum Suppression Accelerator using Multi-Thread Computing and Binary Max Engine for Object Detection. - Chaoming Fang; Habib Derbyshire; Wenyu Sun; Jinshan Yue; Haobing Shi; Yongpan Liu (A-SSCC, 2021)

Challenges and Opportunities of Energy-Efficient CIM SoC Design for Edge AI Devices. - Jinshan Yue; Wenyu Sun; Huazhong Yang; Yongpan Liu (ISOCC, 2021)

A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating. - Jinshan Yue; Xiaoyu Feng; Yifan He 003; Yuxuan Huang; Yipeng Wang 009; Zhe Yuan; Mingtao Zhan; Jiaxin Liu; Jian-Wei Su; Yen-Lin Chung; Ping-Chun Wu; Li-Yang Hung; et al. (ISSCC, 2021)

High Area/Energy Efficiency RRAM CNN Accelerator with Pattern-Pruning-Based Weight Mapping Scheme. - Songming Yu; Lu Zhang 074; Jingyu Wang 004; Jinshan Yue; Zhuqing Yuan; Xueqing Li 002; Huazhong Yang; Yongpan Liu (NVMSA, 2021)

STICKER-T: An Energy-Efficient Neural Network Processor Using Block-Circulant Algorithm and Unified Frequency-Domain Acceleration. - Jinshan Yue; Yongpan Liu; Ruoyang Liu; Wenyu Sun; Zhe Yuan; Yung-Ning Tu; Yi-Ju Chen; Ao Ren; Yanzhi Wang 001; Meng-Fan Chang; Xueqing Li 002; Huazhong Yang (IEEE J. Solid State Circuits, 2021)

RRAM Computing-in-Memory Using Transient Charge Transferring for Low-Power and Small-Latency AI Edge Inference. - Linfang Wang; Junjie An; Wang Ye; Weizeng Li; Hanghang Gao; Yangu He; Jianfeng Gao 005; Jinshan Yue; Lingyan Fan; Chunmeng Dou (APCCAS, 2022)

Sparsity-Aware Non-Volatile Computing-In-Memory Macro with Analog Switch Array and Low-Resolution Current-Mode ADC. - Yuxuan Huang; Yifan He 003; Jinshan Yue; Wenyu Sun; Huazhong Yang; Yongpan Liu (ASP-DAC, 2022)

Toward Low-Bit Neural Network Training Accelerator by Dynamic Group Accumulation. - Yixiong Yang; Ruoyang Liu; Wenyu Sun; Jinshan Yue; Huazhong Yang; Yongpan Liu (ASP-DAC, 2022)

C-RRAM: A Fully Input Parallel Charge-Domain RRAM-based Computing-in-Memory Design with High Tolerance for RRAM Variations. - Yifan He 003; Yuxuan Huang; Jinshan Yue; Wenyu Sun; Lu Zhang 074; Yongpan Liu (ISCAS, 2022)

A 65nm 8b-Activation 8b-Weight SRAM-Based Charge-Domain Computing-in-Memory Macro Using A Fully-Parallel Analog Adder Network and A Single-ADC Interface. - Guodong Yin; Mufeng Zhou; Yiming Chen; Wenjun Tang; Zekun Yang; Mingyen Lee; Xirui Du; Jinshan Yue; Jiaxin Liu; Huazhong Yang; Yongpan Liu; Xueqing Li 002 (CoRR, 2022)

A 65-nm Energy-Efficient Interframe Data Reuse Neural Network Accelerator for Video Applications. - Yixiong Yang; Yongpan Liu; Zhe Yuan; Wenyu Sun; Ruoyang Liu; Jingyu Wang 004; Jinshan Yue; Xiaoyu Feng; Zhuqing Yuan; Xueqing Li 002; Huazhong Yang (IEEE J. Solid State Circuits, 2022)

STICKER-IM: A 65 nm Computing-in-Memory NN Processor Using Block-Wise Sparsity Optimization and Inter/Intra-Macro Data Reuse. - Jinshan Yue; Yongpan Liu; Zhe Yuan; Xiaoyu Feng; Yifan He 002; Wenyu Sun; Zhixiao Zhang; Xin Si; Ruhui Liu; Zi Wang; Meng-Fan Chang; Chunmeng Dou; et al. (IEEE J. Solid State Circuits, 2022)

PACA: A Pattern Pruning Algorithm and Channel-Fused High PE Utilization Accelerator for CNNs. - Jingyu Wang 004; Songming Yu; Zhuqing Yuan; Jinshan Yue; Zhe Yuan; Ruoyang Liu; Yanzhi Wang 001; Huazhong Yang; Xueqing Li 002; Yongpan Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Accuracy Optimization With the Framework of Non-Volatile Computing-In-Memory Systems. - Yuxuan Huang; Yifan He 003; Jinshan Yue; Huazhong Yang; Yongpan Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Bit-Aware Fault-Tolerant Hybrid Retraining and Remapping Schemes for RRAM-Based Computing-in-Memory Systems. - Yuxuan Huang; Yifan He 003; Jingyu Wang 004; Jinshan Yue; Lu Zhang 074; Kaiwei Zou; Huazhong Yang; Yongpan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Demonstration Platform for Large-Scaled Point Cloud Network Based on 28nm 2D/3D Unified Sparse Convolution Accelerator. - Xiaoyu Feng; Wenyu Sun; Shupei Fan; Chen Tang; Yixiong Yang; Jinshan Yue; Qingmin Liao; Huazhong Yang; Yongpan Liu (AICAS, 2023)

A 28nm 1.07TFLOPS/mm2 Dynamic-Precision Training Processor with Online Dynamic Execution and Multi- Level-Aligned Block-FP Processing. - Yixiong Yang; Ruoyang Liu; Chenhan Wei; Wenxun Wang; Wenyu Sun; Jinshan Yue; Huazhong Yang; Yongpan Liu (CICC, 2023)

A User-Friendly Fast and Accurate Simulation Framework for Non-Ideal Factors in Computing-in-Memory Architecture. - Zi Wang; Jinshan Yue; Chaojie He; Zhuoyu Dai; Feibin Xiang; Zhaori Cong; Yifan He 003; Xiaoyu Feng; Yongpan Liu (ISCAS, 2023)

A 28nm 38-to-102-TOPS/W 8b Multiply-Less Approximate Digital SRAM Compute-In-Memory Macro for Neural-Network Inference. - Yifan He 003; Haikang Diao; Chen Tang; Wenbin Jia; Xiyuan Tang; Yuan Wang 001; Jinshan Yue; Xueqing Li 002; Huazhong Yang; Hongyang Jia; Yongpan Liu (ISSCC, 2023)

A 28nm 2D/3D Unified Sparse Convolution Accelerator with Block-Wise Neighbor Searcher for Large-Scaled Voxel-Based Point Cloud Network. - Wenyu Sun; Xiaoyu Feng; Chen Tang; Shupei Fan; Yixiong Yang; Jinshan Yue; Huazhong Yang; Yongpan Liu (ISSCC, 2023)

A 28nm 16.9-300TOPS/W Computing-in-Memory Processor Supporting Floating-Point NN Inference/Training with Intensive-CIM Sparse-Digital Architecture. - Jinshan Yue; Chaojie He; Zi Wang; Zhaori Cong; Yifan He 002; Mufeng Zhou; Wenyu Sun; Xueqing Li 002; Chunmeng Dou; Feng Zhang 014; Huazhong Yang; Yongpan Liu; et al. (ISSCC, 2023)

A 5.6-89.9TOPS/W Heterogeneous Computing-in-Memory SoC with High-Utilization Producer-Consumer Architecture and High-Frequency Read-Free CIM Macro. - Jinshan Yue; Mingtao Zhan; Zi Wang; Yifan He 002; Yaolei Li; Songming Yu; Wenyu Sun; Lu Jie 001; Chunmeng Dou; Xueqing Li 002; Nan Sun 001; Huazhong Yang; et al. (VLSI Technology and Circuits, 2023)

An RRAM-Based Digital Computing-in-Memory Macro With Dynamic Voltage Sense Amplifier and Sparse-Aware Approximate Adder Tree. - Yifan He 003; Jinshan Yue; Xiaoyu Feng; Yuxuan Huang; Hongyang Jia; Jingyu Wang 004; Lu Zhang 074; Wenyu Sun; Huazhong Yang; Yongpan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A Weight-Reload-Eliminated Compute-in-Memory Accelerator for 60 fps 4K Super-Resolution. - Yaolei Li; Jinshan Yue; Jingyu Wang 004; Chen Tang; Yifan He 003; Wenbin Jia; Kaiwei Zou; Lu Zhang 074; Huazhong Yang; Yongpan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

SAMBA: Single-ADC Multi-Bit Accumulation Compute-in-Memory Using Nonlinearity- Compensated Fully Parallel Analog Adder Tree. - Yiming Chen; Guodong Yin; Mufeng Zhou; Wenjun Tang; Zekun Yang; Mingyen Lee; Xirui Du; Jinshan Yue; Jiaxin Liu; Huazhong Yang; Yongpan Liu; Xueqing Li 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A Scalable Small-Footprint Time-Space-Pipelined Architecture for Reservoir Computing. - Zhuoyu Dai; Feibin Xiang; Chaojie He; Zi Wang; Woyu Zhang; Yi Li 049; Jinshan Yue; Dashan Shang (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Recent progress in InGaZnO FETs for high-density 2T0C DRAM applications. - Shengzhe Yan; Zhaori Cong; Nianduan Lu; Jinshan Yue; Qing Luo (Sci. China Inf. Sci., 2023)

A 28-nm RRAM Computing-in-Memory Macro Using Weighted Hybrid 2T1R Cell Array and Reference Subtracting Sense Amplifier for AI Edge Inference. - Wang Ye; Linfang Wang; Zhidao Zhou; Junjie An; Weizeng Li; Hanghang Gao; Zhi Li 062; Jinshan Yue; Hongyang Hu; Xiaoxin Xu; Jianguo Yang; Jing Liu 035; et al. (IEEE J. Solid State Circuits, 2023)

P3 ViT: A CIM-Based High-Utilization Architecture With Dynamic Pruning and Two-Way Ping-Pong Macro for Vision Transformer. - Xiangqu Fu; Qirui Ren; Hao Wu 084; Feibin Xiang; Qing Luo; Jinshan Yue; Yong Chen 005; Feng Zhang 014 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 40-nm SONOS Digital CIM Using Simplified LUT Multiplier and Continuous Sample-Hold Sense Amplifier for AI Edge Inference. - Hongyang Hu; Xiwei Wang; Zi Wang; Haiyang Zhou; Danian Dong; Jinshan Yue; Wan Pang; Xiaoxin Xu; Chunmeng Dou (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A 28nm 8928Kb/mm2-Weight-Density Hybrid SRAM/ROM Compute-in-Memory Architecture Reducing >95% Weight Loading from DRAM. - Guodong Yin; Yiming Chen; Mingyen Lee; Xirui Du; Yue Ke; Wenjun Tang; Zhonghao Chen; Mufeng Zhou; Jinshan Yue; Huazhong Yang; Hongyang Jia; Yongpan Liu; et al. (CICC, 2024)

IG-CRM: Area/Energy-Efficient IGZO-Based Circuits and Architecture Design for Reconfigurable CIM/CAM Applications. - Zeyu Guo 002; Jinshan Yue; Shengzhe Yan; Zhuoyu Dai; Xiangqu Fu; Zhaori Cong; Zening Niu; Ke Hu; Lihua Xu; Jiawei Wang; Lingfei Wang; Guanhua Yang; et al. (DAC, 2024)

A 2T P-Channel Logic Flash Cell for Reconfigurable Interconnection in Chiplet-Based Computing-In-Memory Accelerators. - Weizeng Li; Linfang Wang; Zhi Li 062; Wang Ye; Zhidao Zhou; Haiyang Zhou; Hanghang Gao; Jinshan Yue; Hongyang Hu; Fengman Liu; Qing Luo; Chunmeng Dou (ISCAS, 2024)

34.7 A 28nm 2.4Mb/mm2 6.9 - 16.3TOPS/mm2 eDRAM-LUT-Based Digital-Computing-in-Memory Macro with In-Memory Encoding and Refreshing. - Yifan He 003; Shupei Fan; Xuan Li; Luchang Lei; Wenbin Jia; Chen Tang; Yaolei Li; Zongle Huang; Zhike Du; Jinshan Yue; Xueqing Li 002; Huazhong Yang; et al. (ISSCC, 2024)

34.9 A Flash-SRAM-ADC-Fused Plastic Computing-in-Memory Macro for Learning in Neural Networks in a Standard 14nm FinFET Process. - Linfang Wang; Weizeng Li; Zhidao Zhou; Hanghang Gao; Zhi Li 062; Wang Ye; Hongyang Hu; Jing Liu 035; Jinshan Yue; Jianguo Yang; Qing Luo; Chunmeng Dou; et al. (ISSCC, 2024)

A 41.7TOPS/W@INT8 Computing-in-Memory Processor with Zig-Zag Backbone-Systolic CIM and Block/Self-Gating CAM for NN/Recommendation Applications. - Zhuoyu Dai; Shengzhe Yan; Zhaori Cong; Zeyu Guo 002; Yifan He 002; Wenyu Sun; Chunmeng Dou; Feng Zhang 014; Jinshan Yue; Yongpan Liu; Ming Liu 022 (VLSI Technology and Circuits, 2024)

A 28-nm Computing-in-Memory-Based Super-Resolution Accelerator Incorporating Macro-Level Pipeline and Texture/Algebraic Sparsity. - Hao Wu 084; Yong Chen 005; Yiyang Yuan; Jinshan Yue; Xiangqu Fu; Qirui Ren; Qing Luo; Pui-In Mak; Xinghua Wang; Feng Zhang 014 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

LSAC: A Low-Power Adder Tree for Digital Computing-in-Memory by Sparsity and Approximate Circuits Co-Design. - Chaojie He; Zi Wang; Feibin Xiang; Zhuoyu Dai; Yifan He 003; Jinshan Yue; Yongpan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Write-Verify-Free MLC RRAM Using Nonbinary Encoding for AI Weight Storage at the Edge. - Junjie An; Zhidao Zhou; Linfang Wang; Wang Ye; Weizeng Li; Hanghang Gao; Zhi Li 062; Jinghui Tian; Yan Wang; Hongyang Hu; Jinshan Yue; Lingyan Fan; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2024)

An Energy-Efficient Computing-in-Memory NN Processor With Set-Associate Blockwise Sparsity and Ping-Pong Weight Update. - Jinshan Yue; Yongpan Liu; Xiaoyu Feng; Yifan He 002; Jingyu Wang 004; Zhe Yuan; Mingtao Zhan; Jiaxin Liu; Jian-Wei Su; Yen-Lin Chung; Ping-Chun Wu; Li-Yang Hong; et al. (IEEE J. Solid State Circuits, 2024)

2T2R RRAM-Based In-Memory Hyperdimensional Computing Encoder for Spatio-Temporal Signal Processing. - Zhi Li 070; Rui Bao; Woyu Zhang; Fei Wang; Jun Wang; Renrui Fang; Haoxiong Ren; Ning Lin; Jinshan Yue; Chunmeng Dou; Zhongrui Wang; Dashan Shang (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Fully Binarized Graph Convolutional Network Accelerator Based on In-Memory Computing with Resistive Random-Access Memory. - Woyu Zhang; Zhi Li 070; Xinyuan Zhang 008; Fei Wang; Shaocong Wang; Ning Lin; Yi Li 049; Jun Wang; Jinshan Yue; Chunmeng Dou; Xiaoxin Xu; Zhongrui Wang; et al. (Adv. Intell. Syst., 2024)

A 28-nm Floating-Point Computing-in-Memory Processor Using Intensive-CIM Sparse-Digital Architecture. - Shengzhe Yan; Jinshan Yue; Chaojie He; Zi Wang; Zhaori Cong; Yifan He 002; Mufeng Zhou; Wenyu Sun; Xueqing Li 002; Chunmeng Dou; Feng Zhang 014; Huazhong Yang; et al. (IEEE J. Solid State Circuits, 2024)

A 28-nm Energy-Efficient Sparse Neural Network Processor for Point Cloud Applications Using Block-Wise Online Neighbor Searching. - Xiaoyu Feng; Wenyu Sun; Chen Tang; Xinyuan Lin; Jinshan Yue; Huazhong Yang; Yongpan Liu (IEEE J. Solid State Circuits, 2024)

Hardware Implementation of Next Generation Reservoir Computing with RRAM-Based Hybrid Digital-Analog System. - Danian Dong; Woyu Zhang; Yuanlu Xie; Jinshan Yue; Kuan Ren; Hongjian Huang; Xu Zheng; Wenxuan Sun; Jinru Lai; Shaoyang Fan; Hongzhou Wang; Zhaoan Yu; et al. (Adv. Intell. Syst., 2024)

A Multichiplet Computing-in-Memory Architecture Exploration Framework Based on Various CIM Devices. - Zhuoyu Dai; Feibin Xiang; Xiangqu Fu; Yifan He 003; Wenyu Sun; Yongpan Liu; Guanhua Yang; Feng Zhang 014; Jinshan Yue; Ling Li 013 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Pro-Cache-CIM: A 28nm 69.4TOPS/W Product-Cache-based Digital-Compute-in-Memory Macro Leveraging Data Locality Pattern in Vision AI Tasks. - Wenbin Jia; Yifan He 003; Xiang Li; Yixuan Xie; Zongle Huang; Wenxun Wang; Boju Chen; Yaolei Li; Jinshan Yue; Xueqing Li 002; Huazhong Yang; Hongyang Jia; et al. (CICC, 2025)

Efficient Edge Vision Transformer Accelerator with Decoupled Chunk Attention and Hybrid Computing-In-Memory. - Yi Li 049; Zijian Ye; Xiangqu Fu; Songqi Wang; Shucheng Du; Ning Lin; Dashan Shang; Jinshan Yue; Zhongrui Wang; Xiaojuan Qi 001; Feng Zhang 014; Han Wang (DAC, 2025)

An Energy-Efficient High-Utilization Hardware Architecture for Attention Mechanism in Transformer using Balanced Systolic Array and Multi-Row Interleaved Operation Ordering. - Haiyang Zhou; Hongyang Hu; Jinshan Yue; Hanghang Gao; Yuanlu Xie; Xiaoxin Xu; Chunmeng Dou; Ming Liu 022 (DAC, 2025)

14.5 A 28nm 192.3TFLOPS/W Accurate/Approximate Dual-Mode-Transpose Digital 6T-SRAM CIM Macro for Floating-Point Edge Training and Inference. - Yiyang Yuan; Bingxin Zhang; Yiming Yang; Yishan Luo; Qirui Chen; Shidong Lv; Hao Wu 084; Cailian Ma; Ming Li; Jinshan Yue; Xinghua Wang; Guozhong Xing; et al. (ISSCC, 2025)

A monolithic 3D IGZO-RRAM-SRAM-integrated architecture for robust and efficient compute-in-memory enabling equivalent-ideal device metrics. - Shengzhe Yan; Zhaori Cong; Zi Wang; Zhuoyu Dai; Zeyu Guo 002; Zhihang Qian; Xufan Li; Xu Zheng; Chuanke Chen; Nianduan Lu; Chunmeng Dou; Guanhua Yang; et al. (Sci. China Inf. Sci., 2025)

A 28-nm 19.9-to-258.5-TOPS/W 8b Digital Computing-in-Memory Processor With Two-Cycle Macro Featuring Winograd-Domain Convolution and Macro-Level Parallel Dual-Side Sparsity. - Hao Wu 084; Yong Chen 005; Yiyang Yuan; Jinshan Yue; Xinghua Wang; Xiaoran Li; Feng Zhang 014 (IEEE J. Solid State Circuits, 2025)

A Multiply-Less Approximate SRAM Compute-In-Memory Macro for Neural-Network Inference. - Haikang Diao; Yifan He 003; Xuan Li; Chen Tang; Wenbin Jia; Jinshan Yue; Haoyang Luo; Jiahao Song; Xueqing Li 002; Huazhong Yang; Hongyang Jia; Yongpan Liu; et al. (IEEE J. Solid State Circuits, 2025)

SHMT: An SRAM and HBM Hybrid Computing-in-Memory Architecture With Optimized KV Cache for Multimodal Transformer. - Xiangqu Fu; Jinshan Yue; Muhammad Faizan; Zhi Li 062; Qiang Huo; Feng Zhang 014 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

An RRAM Digital Computing-in-Memory Macro With Dual-Mode Multiplication and Maximum Value Rounding Adder Tree. - Wang Ye; Hanghang Gao; Zhidao Zhou; Linfang Wang; Weizeng Li; Zhi Li 062; Jinshan Yue; Xiaoxin Xu; Jianguo Yang; Hongyang Hu; Chunmeng Dou (IEEE Trans. Very Large Scale Integr. Syst., 2025)

An RRAM-Based Computing-in-Memory Macro With Low-Power Readout/Hold Circuits and Activation Differential Strategy for AdderNet. - Zhihang Qian; Shengzhe Yan; Zhuoyu Dai; Zeyu Guo 002; Zhaori Cong; Yifan He 002; Chunmeng Dou; Feng Zhang 014; Jinshan Yue; Yongpan Liu (IEEE Trans. Very Large Scale Integr. Syst., 2025)

A High-Density Energy-Efficient CNM Macro Using Hybrid RRAM and SRAM for Memory-Bound Applications. - Jun Wang; Shengzhe Yan; Xiangqu Fu; Zhihang Qian; Zhi Li 062; Zeyu Guo 002; Zhuoyu Dai; Zhaori Cong; Chunmeng Dou; Feng Zhang 014; Jinshan Yue; Dashan Shang (IEEE Trans. Very Large Scale Integr. Syst., 2025)

Hybrid SRAM/ROM Compute-in-Memory Architecture for High Task-Level Energy Efficiency in Transformer Models With 8928-kb/mm² Density in 28nm CMOS. - Guodong Yin; Yiming Chen; Mingyen Lee; Xirui Du; Yue Ke; Wenjun Tang; Zhonghao Chen; Mufeng Zhou; Jinshan Yue; Huazhong Yang; Hongyang Jia; Yongpan Liu; et al. (IEEE J. Solid State Circuits, 2025)