A 0.57-GOPS/DSP Object Detection PIM Accelerator on FPGA. - Bo Jiao; Jinshan Zhang 006; Yuanyuan Xie; Shunli Wang 001; Haozhe Zhu; Xiaoyang Kang 001; Zhiyan Dong; Lihua Zhang; Chixiao Chen (ASP-DAC, 2021)

Computing Utilization Enhancement for Chiplet-based Homogeneous Processing-in-Memory Deep Learning Processors. - Bo Jiao; Haozhe Zhu; Jinshan Zhang 006; Shunli Wang 001; Xiaoyang Kang 001; Lihua Zhang; Mingyu Wang 001; Chixiao Chen (ACM Great Lakes Symposium on VLSI, 2021)

ALPINE: An Agile Processing-in-Memory Macro Compilation Framework. - Jinshan Zhang 006; Bo Jiao; Yunzhengmao Wang; Haozhe Zhu; Lihua Zhang; Chixiao Chen (ACM Great Lakes Symposium on VLSI, 2021)

A 11.6μ W Computing-on-Memory-Boundary Keyword Spotting Processor with Joint MFCC-CNN Ternary Quantization. - Xinru Jia; Haozhe Zhu; Yunzheng Wang; Jinshan Zhang 006; Feng Lin; Xiankui Xiong; Dong Xu 015; Chixiao Chen; Qi Liu 010 (ISCAS, 2022)

COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning. - Haozhe Zhu; Bo Jiao; Jinshan Zhang 006; Xinru Jia; Yunzhengmao Wang; Tianchan Guan; Shengcheng Wang; Dimin Niu; Hongzhong Zheng; Chixiao Chen; Mingyu Wang 001; Lihua Zhang; et al. (ISSCC, 2022)

A $2.53 mu mathrm{W}/ text{channel}$ Event-Driven Neural Spike Sorting Processor with Sparsity-Aware Computing-In-Memory Macros. - Hao Jiang 024; Jiapei Zheng; Yunzhengmao Wang; Jinshan Zhang 006; Haozhe Zhu; Liangjian Lyu; Yingping Chen; Chixiao Chen; Qi Liu 010 (ISCAS, 2023)

A Scalable Die-to-Die Interconnect with Replay and Repair Schemes for 2.5D/3D Integration. - Jie Liao; Bo Jiao; Jinshan Zhang 006; Shiwei Liu 002; Hao Jiang 024; Jun Tao 001; Wenning Jiang; Qi Liu 010; Lihua Zhang; Haozhe Zhu; Chixiao Chen (ISCAS, 2023)

A 28nm 53.8TOPS/W 8b Sparse Transformer Accelerator with In-Memory Butterfly Zero Skipper for Unstructured-Pruned NN and CIM-Based Local-Attention-Reusable Engine. - Shiwei Liu 002; Peizhe Li; Jinshan Zhang 006; Yunzhengmao Wang; Haozhe Zhu; Wenning Jiang; Shan Tang; Chixiao Chen; Qi Liu 010; Ming Liu 022 (ISSCC, 2023)

HARDSEA: Hybrid Analog-ReRAM Clustering and Digital-SRAM In-Memory Computing Accelerator for Dynamic Sparse Self-Attention in Transformer. - Shiwei Liu 002; Chen Mu; Hao Jiang 024; Yunzhengmao Wang; Jinshan Zhang 006; Feng Lin; Keji Zhou; Qi Liu 010; Chixiao Chen (IEEE Trans. Very Large Scale Integr. Syst., 2024)