A 5-Gb/s low-power transmitter with voltage-mode output driver in 90nm CMOS technology. - Jinsoo Rhim; Woo-Young Choi (ISOCC, 2011)

A 10-Gb/s power and area efficient clock and data recovery circuit in 65-nm CMOS technology. - Jinsoo Rhim; Kwang-Chun Choi; Woo-Young Choi (ISOCC, 2012)

A 10-Gb/s Adaptive Look-Ahead Decision Feedback Equalizer With an Eye-Opening Monitor. - Chang-Kyung Seong; Jinsoo Rhim; Woo-Young Choi (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

A Low-Voltage PLL With a Supply-Noise Compensated Feedforward Ring VCO. - Sung-Geun Kim; Jinsoo Rhim; Dae Hyun Kwon; Min-Hyeong Kim; Woo-Young Choi (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

A 3D-Integrated 56 Gb/s NRZ/PAM4 Reconfigurable Segmented Mach-Zehnder Modulator-Based Si-Photonics Transmitter. - Cheng Li; Kunzhi Yu; Jinsoo Rhim; Kehan Zhu; Nan Qi; Marco Fiorentino; Thierry Pinguet; Mark Peterson; Vishal Saxena; Samuel Palermo (BCICTS, 2018)