Universal-Vdd 0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell. - Kenichi Osada; Jinuk Luke Shin; Masood Khan; Yude Liou; Karl Wang; Kenichi Shoji; Kenichi Kuroda; Shuji Ikeda; Koichiro Ishibashi (IEEE J. Solid State Circuits, 2001)

Design and implementation of an embedded 512KB level 2 cache subsystem. - Jinuk Luke Shin; Bruce Petrick; Howard Levy; Jinseung Son; Mandeep Singh; Vikas Mathur; Jung-Cheng Yeh; Heesung Choi; Vishal Gupta; Tom Ziaja; Ana Sonia Leon (CICC, 2004)

A dual-core 64b ultraSPARC microprocessor for dense server applications. - Toshinari Takayanagi; Jinuk Luke Shin; Bruce Petrick; Jeffrey Y. Su; Ana Sonia Leon (DAC, 2004)

Design and implementation of an embedded 512-KB level-2 cache subsystem. - Jinuk Luke Shin; Bruce Petrick; Mandeep Singh; Ana Sonia Leon (IEEE J. Solid State Circuits, 2005)

A dual-core 64-bit ultraSPARC microprocessor for dense server applications. - Toshinari Takayanagi; Jinuk Luke Shin; Bruce Petrick; Jeffrey Y. Su; Howard Levy; Ha Pham; Jinseung Son; Nathan Moon; Dina Bistry; Umesh Nair; Mandeep Singh; Vikas Mathur; et al. (IEEE J. Solid State Circuits, 2005)

The UltraSPARC T1 Processor: CMT Reliability. - Ana Sonia Leon; Brian Langley; Jinuk Luke Shin (CICC, 2006)

A Power-Efficient High-Throughput 32-Thread SPARC Processor. - Ana Sonia Leon; Jinuk Luke Shin; Kenway W. Tam; William Bryg; Francis Schumacher; Poonacha Kongetira; David Weisner; Allan Strong (ISSCC, 2006)

A Power-Efficient High-Throughput 32-Thread SPARC Processor. - Ana Sonia Leon; Kenway W. Tam; Jinuk Luke Shin; David Weisner; Francis Schumacher (IEEE J. Solid State Circuits, 2007)

A 40nm 16-core 128-thread CMT SPARC SoC processor. - Jinuk Luke Shin; Kenway W. Tam; Dawei Huang; Bruce Petrick; Ha Pham; Changku Hwang; Hongping Penny Li; Alan P. Smith 002; Timothy Johnson; Francis Schumacher; David Greenhill; Ana Sonia Leon; et al. (ISSCC, 2010)

A 40 nm 16-Core 128-Thread SPARC SoC Processor. - Jinuk Luke Shin; Dawei Huang; Bruce Petrick; Changku Hwang; Kenway W. Tam; Alan P. Smith 002; Ha Pham; Hongping Penny Li; Timothy Johnson; Francis Schumacher; Ana Sonia Leon; Allan Strong (IEEE J. Solid State Circuits, 2011)

Session 3 overview: Processors: High performance digital subcommittee. - Joshua Friedrich; Jinuk Luke Shin (ISSCC, 2012)

The next-generation 64b SPARC core in a T4 SoC processor. - Jinuk Luke Shin; Heechoul Park; Hongping Penny Li; Alan P. Smith 002; Youngmoon Choi; Harikaran Sathianathan; Sudesna Dash; Sebastian Turullols; Song Kim; Robert P. Masleid; Georgios K. Konstadinidis; Robert T. Golla; et al. (ISSCC, 2012)

3.6GHz 16-core SPARC SoC processor in 28nm. - Jason Hart; Steve Butler; Hoyeol Cho; Yuefei Ge; Gregory Gruber; Dawei Huang; Changku Hwang; Daisy Jian; Timothy Johnson; Georgios K. Konstadinidis; Lance Kwong; Robert P. Masleid; et al. (ISSCC, 2013)

Bandwidth and power management of glueless 8-socket SPARC T5 system. - Venkatram Krishnaswamy; Dawei Huang; Sebastian Turullols; Jinuk Luke Shin (ISSCC, 2013)

The Next Generation 64b SPARC Core in a T4 SoC Processor. - Jinuk Luke Shin; Robert T. Golla; Hongping Penny Li; Sudesna Dash; Youngmoon Choi; Alan P. Smith 002; Harikaran Sathianathan; Mayur Joshi; Heechoul Park; Mohamed Elgebaly; Sebastian Turullols; Song Kim; et al. (IEEE J. Solid State Circuits, 2013)

Asymmetric Frequency Locked Loop (AFLL) for adaptive clock generation in a 28nm SPARC M6 processor. - Yifan YangGong; Sebastian Turullols; Daniel Woo; Changku Huang; King C. Yen; Venkatram Krishnaswamy; Kalon Holdbrook; Jinuk Luke Shin (A-SSCC, 2014)

A 3.6 GHz 16-Core SPARC SoC Processor in 28 nm. - Jason Hart; Hoyeol Cho; Yuefei Ge; Gregory Gruber; Dawei Huang; Changku Hwang; Daisy Jian; Timothy Johnson; Georgios K. Konstadinidis; Venkatram Krishnaswamy; Lance Kwong; Robert P. Masleid; et al. (IEEE J. Solid State Circuits, 2014)

Session 4 overview: Processors: High-performance digital subcommittee. - Atsuki Inoue; Jinuk Luke Shin (ISSCC, 2015)

4.3 Fine-grained adaptive power management of the SPARC M7 processor. - Venkatram Krishnaswamy; Jeffrey Brooks; Georgios K. Konstadinidis; Curtis McAllister; Ha Pham; Sebastian Turullols; Jinuk Luke Shin; Yifan YangGong; Haowei Zhang (ISSCC, 2015)

4.2 A 20nm 32-Core 64MB L3 cache SPARC M7 processor. - Penny Li; Jinuk Luke Shin; Georgios K. Konstadinidis; Francis Schumacher; Venkatram Krishnaswamy; Hoyeol Cho; Sudesna Dash; Robert P. Masleid; Chaoyang Zheng; Yuanjung David Lin; Paul Loewenstein; Heechoul Park; et al. (ISSCC, 2015)

Introduction to the January Special Issue on the 2015 IEEE International Solid-State Circuits Conference. - Edith Beigné; Jinuk Luke Shin; Yusuke Oike; Chulwoo Kim; Jan Genoe (IEEE J. Solid State Circuits, 2016)

SambaNova SN10 RDU: A 7nm Dataflow Architecture to Accelerate Software 2.0. - Raghu Prabhakar; Sumti Jairath; Jinuk Luke Shin (ISSCC, 2022)

AI SoC Design Challenges in the Foundation Model Era. - Zhengyu Chen 002; Dawei Huang; Mingran Wang; Bowen Yang; Jinuk Luke Shin; Changran Hu; Bo Li 005; Raghu Prabhakar; Gao Deng; Yongning Sheng; Sihua Fu; Lu Yuan; et al. (CICC, 2023)

16.4: SambaNova SN40L: A 5nm 2.5D Dataflow Accelerator with Three Memory Tiers for Trillion Parameter AI. - Raghu Prabhakar; Junwei Zhou; Darshan Gandhi; Youngmoon Choi; Mahmood Khayatzadeh; Kyunglok Kim; Uma Durairajan; Jeongha Park; Satyajit Sarkar; Jinuk Luke Shin (ISSCC, 2025)