HiVeGen - Hierarchical LLM-based Verilog Generation for Scalable Chip Design. - Jinwei Tang; Jiayin Qin; Kiran Thorat; Chen Tian 001; Yu Cao; Yang Zhao; Caiwen Ding (CoRR, 2024)

MAHL: Multi-Agent LLM-Guided Hierarchical Chiplet Design with Adaptive Debugging. - Jinwei Tang; Jiayin Qin; Nuo Xu; Pragnya Sudershan Nalla; Yu Cao; Yang Zhao; Caiwen Ding (CoRR, 2025)