14.4 A 5GHz -95dBc-reference-Spur 9.5mW digital fractional-N PLL using reference-multiplied time-to-digital converter and reference-spur cancellation in 65nm CMOS. - Hyojun Kim; Jinwoo Sang; Hyunik Kim; Youngwoo Jo; Taeik Kim; Hojin Park; SeongHwan Cho (ISSCC, 2015)